LXR uboot/arch/powerpc/cpu/mpc83xx/pcie.c

   1/*
   2 * Copyright (C) 2007-2009  Freescale Semiconductor, Inc.
   3 * Copyright (C) 2008-2009  MontaVista Software, Inc.
   4 *
   5 * Authors: Tony Li <tony.li@freescale.com>
   6 *          Anton Vorontsov <avorontsov@ru.mvista.com>
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <pci.h>
  26#include <mpc83xx.h>
  27#include <asm/io.h>
  28
  29DECLARE_GLOBAL_DATA_PTR;
  30
  31#define PCIE_MAX_BUSES 2
  32
  33static struct {
  34        u32 base;
  35        u32 size;
  36} mpc83xx_pcie_cfg_space[] = {
  37        {
  38                .base = CONFIG_SYS_PCIE1_CFG_BASE,
  39                .size = CONFIG_SYS_PCIE1_CFG_SIZE,
  40        },
  41#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
  42        {
  43                .base = CONFIG_SYS_PCIE2_CFG_BASE,
  44                .size = CONFIG_SYS_PCIE2_CFG_SIZE,
  45        },
  46#endif
  47};
  48
  49#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
  50
  51/* private structure for mpc83xx pcie hose */
  52static struct mpc83xx_pcie_priv {
  53        u8 index;
  54} pcie_priv[PCIE_MAX_BUSES] = {
  55        {
  56                /* pcie controller 1 */
  57                .index = 0,
  58        },
  59        {
  60                /* pcie controller 2 */
  61                .index = 1,
  62        },
  63};
  64
  65static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
  66{
  67        int bus = PCI_BUS(dev) - hose->first_busno;
  68        immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  69        struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
  70        pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
  71        struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
  72        u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
  73        u32 dev_base = bus << 24 | devfn << 16;
  74
  75        if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
  76                return -1;
  77        /*
  78         * Workaround for the HW bug: for Type 0 configure transactions the
  79         * PCI-E controller does not check the device number bits and just
  80         * assumes that the device number bits are 0.
  81         */
  82        if (devfn & 0xf8)
  83                return -1;
  84
  85        out_le32(&out_win->tarl, dev_base);
  86        return 0;
  87}
  88
  89#define cfg_read(val, addr, type, op) \
  90        do { *val = op((type)(addr)); } while (0)
  91#define cfg_write(val, addr, type, op) \
  92        do { op((type *)(addr), (val)); } while (0)
  93
  94#define cfg_read_err(val) do { *val = -1; } while (0)
  95#define cfg_write_err(val) do { } while (0)
  96
  97#define PCIE_OP(rw, size, type, op)                                     \
  98static int pcie_##rw##_config_##size(struct pci_controller *hose,       \
  99                                     pci_dev_t dev, int offset,         \
 100                                     type val)                          \
 101{                                                                       \
 102        int ret;                                                        \
 103                                                                        \
 104        ret = mpc83xx_pcie_remap_cfg(hose, dev);                        \
 105        if (ret) {                                                      \
 106                cfg_##rw##_err(val);                                    \
 107                return ret;                                             \
 108        }                                                               \
 109        cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op);       \
 110        return 0;                                                       \
 111}
 112
 113PCIE_OP(read, byte, u8 *, in_8)
 114PCIE_OP(read, word, u16 *, in_le16)
 115PCIE_OP(read, dword, u32 *, in_le32)
 116PCIE_OP(write, byte, u8, out_8)
 117PCIE_OP(write, word, u16, out_le16)
 118PCIE_OP(write, dword, u32, out_le32)
 119
 120static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 121                                       u8 link)
 122{
 123        extern void disable_addr_trans(void); /* start.S */
 124        static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
 125        struct pci_controller *hose = &pcie_hose[bus];
 126        int i;
 127
 128        /*
 129         * There are no spare BATs to remap all PCI-E windows for U-Boot, so
 130         * disable translations. In general, this is not great solution, and
 131         * that's why we don't register PCI-E hoses by default.
 132         */
 133        disable_addr_trans();
 134
 135        for (i = 0; i < 2; i++, reg++) {
 136                if (reg->size == 0)
 137                        break;
 138
 139                hose->regions[i] = *reg;
 140                hose->region_count++;
 141        }
 142
 143        i = hose->region_count++;
 144        hose->regions[i].bus_start = 0;
 145        hose->regions[i].phys_start = 0;
 146        hose->regions[i].size = gd->ram_size;
 147        hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
 148
 149        i = hose->region_count++;
 150        hose->regions[i].bus_start = CONFIG_SYS_IMMR;
 151        hose->regions[i].phys_start = CONFIG_SYS_IMMR;
 152        hose->regions[i].size = 0x100000;
 153        hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
 154
 155        hose->first_busno = pci_last_busno() + 1;
 156        hose->last_busno = 0xff;
 157
 158        hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
 159
 160        hose->priv_data = &pcie_priv[bus];
 161
 162        pci_set_ops(hose,
 163                        pcie_read_config_byte,
 164                        pcie_read_config_word,
 165                        pcie_read_config_dword,
 166                        pcie_write_config_byte,
 167                        pcie_write_config_word,
 168                        pcie_write_config_dword);
 169
 170        if (!link)
 171                hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
 172
 173        pci_register_hose(hose);
 174
 175#ifdef CONFIG_PCI_SCAN_SHOW
 176        printf("PCI:   Bus Dev VenId DevId Class Int\n");
 177#endif
 178        /*
 179         * Hose scan.
 180         */
 181        hose->last_busno = pci_hose_scan(hose);
 182}
 183
 184#else
 185
 186static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 187                                       u8 link) {}
 188
 189#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
 190
 191static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
 192{
 193        immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 194        pex83xx_t *pex = &immr->pciexp[bus];
 195        struct pex_outbound_window *out_win;
 196        struct pex_inbound_window *in_win;
 197        void *hose_cfg_base;
 198        unsigned int ram_sz;
 199        unsigned int barl;
 200        unsigned int tar;
 201        u16 reg16;
 202        int i;
 203
 204        /* Enable pex csb bridge inbound & outbound transactions */
 205        out_le32(&pex->bridge.pex_csb_ctrl,
 206                in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
 207                PEX_CSB_CTRL_IBPIOE);
 208
 209        /* Enable bridge outbound */
 210        out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
 211                PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
 212                PEX_CSB_OBCTRL_CFGWE);
 213
 214        out_win = &pex->bridge.pex_outbound_win[0];
 215        out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
 216                        mpc83xx_pcie_cfg_space[bus].size);
 217        out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
 218        out_le32(&out_win->tarl, 0);
 219        out_le32(&out_win->tarh, 0);
 220
 221        for (i = 0; i < 2; i++) {
 222                u32 ar;
 223
 224                if (reg[i].size == 0)
 225                        break;
 226
 227                out_win = &pex->bridge.pex_outbound_win[i + 1];
 228                out_le32(&out_win->bar, reg[i].phys_start);
 229                out_le32(&out_win->tarl, reg[i].bus_start);
 230                out_le32(&out_win->tarh, 0);
 231                ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
 232                if (reg[i].flags & PCI_REGION_IO)
 233                        ar |= PEX_OWAR_TYPE_IO;
 234                else
 235                        ar |= PEX_OWAR_TYPE_MEM;
 236                out_le32(&out_win->ar, ar);
 237        }
 238
 239        out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
 240
 241        ram_sz = gd->ram_size;
 242        barl = 0;
 243        tar = 0;
 244        i = 0;
 245        while (ram_sz > 0) {
 246                in_win = &pex->bridge.pex_inbound_win[i];
 247                out_le32(&in_win->barl, barl);
 248                out_le32(&in_win->barh, 0x0);
 249                out_le32(&in_win->tar, tar);
 250                if (ram_sz >= 0x10000000) {
 251                        /* The maxium windows size is 256M */
 252                        out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
 253                                PEX_IWAR_TYPE_PF | 0x0FFFF000);
 254                        barl += 0x10000000;
 255                        tar += 0x10000000;
 256                        ram_sz -= 0x10000000;
 257                } else {
 258                        /* The UM  is not clear here.
 259                         * So, round up to even Mb boundary */
 260
 261                        ram_sz = ram_sz >> (20 +
 262                                        ((ram_sz & 0xFFFFF) ? 1 : 0));
 263                        if (!(ram_sz % 2))
 264                                ram_sz -= 1;
 265                        out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
 266                                PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
 267                        ram_sz = 0;
 268                }
 269                i++;
 270        }
 271
 272        in_win = &pex->bridge.pex_inbound_win[i];
 273        out_le32(&in_win->barl, CONFIG_SYS_IMMR);
 274        out_le32(&in_win->barh, 0);
 275        out_le32(&in_win->tar, CONFIG_SYS_IMMR);
 276        out_le32(&in_win->ar, PEX_IWAR_EN |
 277                PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
 278
 279        /* Enable the host virtual INTX interrupts */
 280        out_le32(&pex->bridge.pex_int_axi_misc_enb,
 281                in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
 282
 283        /* Hose configure header is memory-mapped */
 284        hose_cfg_base = (void *)pex;
 285
 286        get_clocks();
 287        /* Configure the PCIE controller core clock ratio */
 288        out_le32(hose_cfg_base + PEX_GCLK_RATIO,
 289                (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
 290                        / 1000000) * 16) / 333);
 291        udelay(1000000);
 292
 293        /* Do Type 1 bridge configuration */
 294        out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
 295        out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
 296        out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
 297
 298        /*
 299         * Write to Command register
 300         */
 301        reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
 302        reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
 303                        PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
 304        out_le16(hose_cfg_base + PCI_COMMAND, reg16);
 305
 306        /*
 307         * Clear non-reserved bits in status register.
 308         */
 309        out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
 310        out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
 311        out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
 312
 313        printf("PCIE%d: ", bus);
 314
 315        reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
 316        if (reg16 >= PCI_LTSSM_L0)
 317                printf("link\n");
 318        else
 319                printf("No link\n");
 320
 321        mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
 322}
 323
 324/*
 325 * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
 326 * must have been set to cover all of the requested regions.
 327 */
 328void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
 329{
 330        int i;
 331
 332        /*
 333         * Release PCI RST Output signal.
 334         * Power on to RST high must be at least 100 ms as per PCI spec.
 335         * On warm boots only 1 ms is required, but we play it safe.
 336         */
 337        udelay(100000);
 338
 339        if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
 340                printf("Second PCIE host contoller not configured!\n");
 341                num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
 342        }
 343
 344        for (i = 0; i < num_buses; i++)
 345                mpc83xx_pcie_init_bus(i, reg[i]);
 346}
 347