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28#include <config.h>
29#include <common.h>
30#include <watchdog.h>
31#include <command.h>
32#include <fsl_esdhc.h>
33#include <asm/cache.h>
34#include <asm/io.h>
35#include <asm/mmu.h>
36#include <asm/fsl_ifc.h>
37#include <asm/fsl_law.h>
38#include <asm/fsl_lbc.h>
39#include <post.h>
40#include <asm/processor.h>
41#include <asm/fsl_ddr_sdram.h>
42
43DECLARE_GLOBAL_DATA_PTR;
44
45
46
47
48static void
49__board_reset(void)
50{
51
52}
53void board_reset(void) __attribute__((weak, alias("__board_reset")));
54
55int checkcpu (void)
56{
57 sys_info_t sysinfo;
58 uint pvr, svr;
59 uint ver;
60 uint major, minor;
61 struct cpu_type *cpu;
62 char buf1[32], buf2[32];
63#if (defined(CONFIG_DDR_CLK_FREQ) || \
64 defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
65 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
66#endif
67
68
69
70
71
72
73#ifdef CONFIG_FSL_CORENET
74#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
75 u32 ddr_sync = 0;
76#else
77 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
78 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
79#endif
80#else
81#ifdef CONFIG_DDR_CLK_FREQ
82 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
83 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
84#else
85 u32 ddr_ratio = 0;
86#endif
87#endif
88
89 unsigned int i, core, nr_cores = cpu_numcores();
90 u32 mask = cpu_mask();
91
92 svr = get_svr();
93 major = SVR_MAJ(svr);
94 minor = SVR_MIN(svr);
95
96 if (cpu_numcores() > 1) {
97#ifndef CONFIG_MP
98 puts("Unicore software on multiprocessor system!!\n"
99 "To enable mutlticore build define CONFIG_MP\n");
100#endif
101 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
102 printf("CPU%d: ", pic->whoami);
103 } else {
104 puts("CPU: ");
105 }
106
107 cpu = gd->arch.cpu;
108
109 puts(cpu->name);
110 if (IS_E_PROCESSOR(svr))
111 puts("E");
112
113 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
114
115 pvr = get_pvr();
116 ver = PVR_VER(pvr);
117 major = PVR_MAJ(pvr);
118 minor = PVR_MIN(pvr);
119
120 printf("Core: ");
121 switch(ver) {
122 case PVR_VER_E500_V1:
123 case PVR_VER_E500_V2:
124 puts("E500");
125 break;
126 case PVR_VER_E500MC:
127 puts("E500MC");
128 break;
129 case PVR_VER_E5500:
130 puts("E5500");
131 break;
132 case PVR_VER_E6500:
133 puts("E6500");
134 break;
135 default:
136 puts("Unknown");
137 break;
138 }
139
140 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
141
142 if (nr_cores > CONFIG_MAX_CPUS) {
143 panic("\nUnexpected number of cores: %d, max is %d\n",
144 nr_cores, CONFIG_MAX_CPUS);
145 }
146
147 get_sys_info(&sysinfo);
148
149 puts("Clock Configuration:");
150 for_each_cpu(i, core, nr_cores, mask) {
151 if (!(i & 3))
152 printf ("\n ");
153 printf("CPU%d:%-4s MHz, ", core,
154 strmhz(buf1, sysinfo.freqProcessor[core]));
155 }
156 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
157
158#ifdef CONFIG_FSL_CORENET
159 if (ddr_sync == 1) {
160 printf(" DDR:%-4s MHz (%s MT/s data rate) "
161 "(Synchronous), ",
162 strmhz(buf1, sysinfo.freqDDRBus/2),
163 strmhz(buf2, sysinfo.freqDDRBus));
164 } else {
165 printf(" DDR:%-4s MHz (%s MT/s data rate) "
166 "(Asynchronous), ",
167 strmhz(buf1, sysinfo.freqDDRBus/2),
168 strmhz(buf2, sysinfo.freqDDRBus));
169 }
170#else
171 switch (ddr_ratio) {
172 case 0x0:
173 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
174 strmhz(buf1, sysinfo.freqDDRBus/2),
175 strmhz(buf2, sysinfo.freqDDRBus));
176 break;
177 case 0x7:
178 printf(" DDR:%-4s MHz (%s MT/s data rate) "
179 "(Synchronous), ",
180 strmhz(buf1, sysinfo.freqDDRBus/2),
181 strmhz(buf2, sysinfo.freqDDRBus));
182 break;
183 default:
184 printf(" DDR:%-4s MHz (%s MT/s data rate) "
185 "(Asynchronous), ",
186 strmhz(buf1, sysinfo.freqDDRBus/2),
187 strmhz(buf2, sysinfo.freqDDRBus));
188 break;
189 }
190#endif
191
192#if defined(CONFIG_FSL_LBC)
193 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
194 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
195 } else {
196 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
197 sysinfo.freqLocalBus);
198 }
199#endif
200
201#if defined(CONFIG_FSL_IFC)
202 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
203#endif
204
205#ifdef CONFIG_CPM2
206 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
207#endif
208
209#ifdef CONFIG_QE
210 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
211#endif
212
213#ifdef CONFIG_SYS_DPAA_FMAN
214 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
215 printf(" FMAN%d: %s MHz\n", i + 1,
216 strmhz(buf1, sysinfo.freqFMan[i]));
217 }
218#endif
219
220#ifdef CONFIG_SYS_DPAA_QBMAN
221 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
222#endif
223
224#ifdef CONFIG_SYS_DPAA_PME
225 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
226#endif
227
228 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
229
230 return 0;
231}
232
233
234
235
236int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
237{
238
239#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
240 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
241 unsigned long val, msr;
242
243
244
245
246
247 msr = mfmsr ();
248 msr |= MSR_DE;
249 mtmsr (msr);
250
251 val = mfspr(DBCR0);
252 val |= 0x70000000;
253 mtspr(DBCR0,val);
254#else
255 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
256
257
258 board_reset();
259
260
261 out_be32(&gur->rstcr, 0x2);
262 udelay(100);
263#endif
264
265 return 1;
266}
267
268
269
270
271
272#ifndef CONFIG_SYS_FSL_TBCLK_DIV
273#define CONFIG_SYS_FSL_TBCLK_DIV 8
274#endif
275unsigned long get_tbclk (void)
276{
277 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
278
279 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
280}
281
282
283#if defined(CONFIG_WATCHDOG)
284void
285watchdog_reset(void)
286{
287 int re_enable = disable_interrupts();
288 reset_85xx_watchdog();
289 if (re_enable) enable_interrupts();
290}
291
292void
293reset_85xx_watchdog(void)
294{
295
296
297
298 mtspr(SPRN_TSR, TSR_WIS);
299}
300#endif
301
302
303
304
305
306int cpu_mmc_init(bd_t *bis)
307{
308#ifdef CONFIG_FSL_ESDHC
309 return fsl_esdhc_mmc_init(bis);
310#else
311 return 0;
312#endif
313}
314
315
316
317
318
319
320void mpc85xx_reginfo(void)
321{
322 print_tlbcam();
323 print_laws();
324#if defined(CONFIG_FSL_LBC)
325 print_lbc_regs();
326#endif
327#ifdef CONFIG_FSL_IFC
328 print_ifc_regs();
329#endif
330
331}
332
333
334#ifndef CONFIG_FSL_CORENET
335#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
336 !defined(CONFIG_SYS_INIT_L2_ADDR)
337phys_size_t initdram(int board_type)
338{
339#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
340 return fsl_ddr_sdram_size();
341#else
342 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
343#endif
344}
345#else
346phys_size_t initdram(int board_type)
347{
348 phys_size_t dram_size = 0;
349
350#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
351 {
352 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
353 unsigned int x = 10;
354 unsigned int i;
355
356
357
358
359 out_be32(&gur->ddrdllcr, 0x81000000);
360 asm("sync;isync;msync");
361 udelay(200);
362 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
363 setbits_be32(&gur->devdisr, 0x00010000);
364 for (i = 0; i < x; i++)
365 ;
366 clrbits_be32(&gur->devdisr, 0x00010000);
367 x++;
368 }
369 }
370#endif
371
372#if defined(CONFIG_SPD_EEPROM) || \
373 defined(CONFIG_DDR_SPD) || \
374 defined(CONFIG_SYS_DDR_RAW_TIMING)
375 dram_size = fsl_ddr_sdram();
376#else
377 dram_size = fixed_sdram();
378#endif
379 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
380 dram_size *= 0x100000;
381
382#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
383
384
385
386 ddr_enable_ecc(dram_size);
387#endif
388
389#if defined(CONFIG_FSL_LBC)
390
391 lbc_sdram_init();
392#endif
393
394 debug("DDR: ");
395 return dram_size;
396}
397#endif
398#endif
399
400#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
401
402
403void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
404 unsigned int ctrl_num);
405void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
406 phys_addr_t *rpn);
407unsigned int
408 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
409
410void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
411
412static void dump_spd_ddr_reg(void)
413{
414 int i, j, k, m;
415 u8 *p_8;
416 u32 *p_32;
417 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
418 generic_spd_eeprom_t
419 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
420
421 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
422 fsl_ddr_get_spd(spd[i], i);
423
424 puts("SPD data of all dimms (zero vaule is omitted)...\n");
425 puts("Byte (hex) ");
426 k = 1;
427 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
428 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
429 printf("Dimm%d ", k++);
430 }
431 puts("\n");
432 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
433 m = 0;
434 printf("%3d (0x%02x) ", k, k);
435 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
436 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
437 p_8 = (u8 *) &spd[i][j];
438 if (p_8[k]) {
439 printf("0x%02x ", p_8[k]);
440 m++;
441 } else
442 puts(" ");
443 }
444 }
445 if (m)
446 puts("\n");
447 else
448 puts("\r");
449 }
450
451 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
452 switch (i) {
453 case 0:
454 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
455 break;
456#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
457 case 1:
458 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
459 break;
460#endif
461#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
462 case 2:
463 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
464 break;
465#endif
466#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
467 case 3:
468 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
469 break;
470#endif
471 default:
472 printf("%s unexpected controller number = %u\n",
473 __func__, i);
474 return;
475 }
476 }
477 printf("DDR registers dump for all controllers "
478 "(zero vaule is omitted)...\n");
479 puts("Offset (hex) ");
480 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
481 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
482 puts("\n");
483 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
484 m = 0;
485 printf("%6d (0x%04x)", k * 4, k * 4);
486 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
487 p_32 = (u32 *) ddr[i];
488 if (p_32[k]) {
489 printf(" 0x%08x", p_32[k]);
490 m++;
491 } else
492 puts(" ");
493 }
494 if (m)
495 puts("\n");
496 else
497 puts("\r");
498 }
499 puts("\n");
500}
501
502
503static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
504{
505 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
506 unsigned long epn;
507 u32 tsize, valid, ptr;
508 int ddr_esel;
509
510 clear_ddr_tlbs_phys(p_addr, size>>20);
511
512
513 setup_ddr_tlbs_phys(p_addr, size>>20);
514
515 ptr = vstart;
516 ddr_esel = find_tlb_idx((void *)ptr, 1);
517 if (ddr_esel != -1) {
518 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
519 } else {
520 printf("TLB error in function %s\n", __func__);
521 return -1;
522 }
523
524 return 0;
525}
526
527
528
529
530
531
532int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
533{
534 phys_addr_t test_cap, p_addr;
535 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
536
537#if !defined(CONFIG_PHYS_64BIT) || \
538 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
539 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
540 test_cap = p_size;
541#else
542 test_cap = gd->ram_size;
543#endif
544 p_addr = (*vstart) + (*size) + (*phys_offset);
545 if (p_addr < test_cap - 1) {
546 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
547 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
548 return -1;
549 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
550 *size = (u32) p_size;
551 printf("Testing 0x%08llx - 0x%08llx\n",
552 (u64)(*vstart) + (*phys_offset),
553 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
554 } else
555 return 1;
556
557 return 0;
558}
559
560
561int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
562{
563 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
564
565 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
566 *size = (u32) p_size;
567 *phys_offset = 0;
568
569#if !defined(CONFIG_PHYS_64BIT) || \
570 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
571 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
572 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
573 puts("Cannot test more than ");
574 print_size(CONFIG_MAX_MEM_MAPPED,
575 " without proper 36BIT support.\n");
576 }
577#endif
578 printf("Testing 0x%08llx - 0x%08llx\n",
579 (u64)(*vstart) + (*phys_offset),
580 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
581
582 return 0;
583}
584
585
586int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
587{
588 unsigned long epn;
589 u32 tsize, valid, ptr;
590 phys_addr_t rpn = 0;
591 int ddr_esel;
592
593
594 ptr = *vstart;
595
596 while (ptr < (*vstart) + (*size)) {
597 ddr_esel = find_tlb_idx((void *)ptr, 1);
598 if (ddr_esel != -1) {
599 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
600 disable_tlb(ddr_esel);
601 }
602 ptr += TSIZE_TO_BYTES(tsize);
603 }
604
605 puts("Remap DDR ");
606 setup_ddr_tlbs(gd->ram_size>>20);
607 puts("\n");
608
609 return 0;
610}
611
612void arch_memory_failure_handle(void)
613{
614 dump_spd_ddr_reg();
615}
616#endif
617
