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15#ifndef __CPM_85XX__
16#define __CPM_85XX__
17
18#include <asm/immap_85xx.h>
19
20
21
22#define CPM_CR_RST ((uint)0x80000000)
23#define CPM_CR_PAGE ((uint)0x7c000000)
24#define CPM_CR_SBLOCK ((uint)0x03e00000)
25#define CPM_CR_FLG ((uint)0x00010000)
26#define CPM_CR_MCN ((uint)0x00003fc0)
27#define CPM_CR_OPCODE ((uint)0x0000000f)
28
29
30
31#define CPM_CR_SCC1_SBLOCK (0x04)
32#define CPM_CR_SCC2_SBLOCK (0x05)
33#define CPM_CR_SCC3_SBLOCK (0x06)
34#define CPM_CR_SCC4_SBLOCK (0x07)
35#define CPM_CR_SMC1_SBLOCK (0x08)
36#define CPM_CR_SMC2_SBLOCK (0x09)
37#define CPM_CR_SPI_SBLOCK (0x0a)
38#define CPM_CR_I2C_SBLOCK (0x0b)
39#define CPM_CR_TIMER_SBLOCK (0x0f)
40#define CPM_CR_RAND_SBLOCK (0x0e)
41#define CPM_CR_FCC1_SBLOCK (0x10)
42#define CPM_CR_FCC2_SBLOCK (0x11)
43#define CPM_CR_FCC3_SBLOCK (0x12)
44#define CPM_CR_MCC1_SBLOCK (0x1c)
45
46#define CPM_CR_SCC1_PAGE (0x00)
47#define CPM_CR_SCC2_PAGE (0x01)
48#define CPM_CR_SCC3_PAGE (0x02)
49#define CPM_CR_SCC4_PAGE (0x03)
50#define CPM_CR_SPI_PAGE (0x09)
51#define CPM_CR_I2C_PAGE (0x0a)
52#define CPM_CR_TIMER_PAGE (0x0a)
53#define CPM_CR_RAND_PAGE (0x0a)
54#define CPM_CR_FCC1_PAGE (0x04)
55#define CPM_CR_FCC2_PAGE (0x05)
56#define CPM_CR_FCC3_PAGE (0x06)
57#define CPM_CR_MCC1_PAGE (0x07)
58#define CPM_CR_MCC2_PAGE (0x08)
59
60
61
62#define CPM_CR_INIT_TRX ((ushort)0x0000)
63#define CPM_CR_INIT_RX ((ushort)0x0001)
64#define CPM_CR_INIT_TX ((ushort)0x0002)
65#define CPM_CR_HUNT_MODE ((ushort)0x0003)
66#define CPM_CR_STOP_TX ((ushort)0x0004)
67#define CPM_CR_RESTART_TX ((ushort)0x0006)
68#define CPM_CR_SET_GADDR ((ushort)0x0008)
69
70#define mk_cr_cmd(PG, SBC, MCN, OP) \
71 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
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77
78
79#define CPM_DATAONLY_BASE ((uint)128)
80#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
81#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
82#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
83#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
84#else
85#define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000)
86#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
87#endif
88
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91
92
93#define NUM_CPM_HOST_PAGES 2
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98
99uint m8560_cpm_dpalloc(uint size, uint align);
100uint m8560_cpm_hostalloc(uint size, uint align);
101void m8560_cpm_setbrg(uint brg, uint rate);
102void m8560_cpm_fastbrg(uint brg, uint rate, int div16);
103void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
104
105
106
107typedef struct cpm_buf_desc {
108 ushort cbd_sc;
109 ushort cbd_datlen;
110 uint cbd_bufaddr;
111} cbd_t;
112
113#define BD_SC_EMPTY ((ushort)0x8000)
114#define BD_SC_READY ((ushort)0x8000)
115#define BD_SC_WRAP ((ushort)0x2000)
116#define BD_SC_INTRPT ((ushort)0x1000)
117#define BD_SC_LAST ((ushort)0x0800)
118#define BD_SC_CM ((ushort)0x0200)
119#define BD_SC_ID ((ushort)0x0100)
120#define BD_SC_P ((ushort)0x0100)
121#define BD_SC_BR ((ushort)0x0020)
122#define BD_SC_FR ((ushort)0x0010)
123#define BD_SC_PR ((ushort)0x0008)
124#define BD_SC_OV ((ushort)0x0002)
125#define BD_SC_CD ((ushort)0x0001)
126
127
128
129#define CPMFCR_GBL ((u_char)0x20)
130#define CPMFCR_EB ((u_char)0x10)
131#define CPMFCR_TC2 ((u_char)0x04)
132#define CPMFCR_DTB ((u_char)0x02)
133#define CPMFCR_BDB ((u_char)0x01)
134
135
136
137#define CPM_POST_WORD_ADDR 0x80FC
138#define PROFF_SCC1 ((uint)0x8000)
139#define PROFF_SCC2 ((uint)0x8100)
140#define PROFF_SCC3 ((uint)0x8200)
141#define PROFF_SCC4 ((uint)0x8300)
142#define PROFF_FCC1 ((uint)0x8400)
143#define PROFF_FCC2 ((uint)0x8500)
144#define PROFF_FCC3 ((uint)0x8600)
145#define PROFF_MCC1 ((uint)0x8700)
146#define PROFF_MCC2 ((uint)0x8800)
147#define PROFF_SPI_BASE ((uint)0x89fc)
148#define PROFF_TIMERS ((uint)0x8ae0)
149#define PROFF_REVNUM ((uint)0x8af0)
150#define PROFF_RAND ((uint)0x8af8)
151#define PROFF_I2C_BASE ((uint)0x8afc)
152
153
154
155#define CPM_BRG_RST ((uint)0x00020000)
156#define CPM_BRG_EN ((uint)0x00010000)
157#define CPM_BRG_EXTC_INT ((uint)0x00000000)
158#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
159#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
160#define CPM_BRG_ATB ((uint)0x00002000)
161#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
162#define CPM_BRG_DIV16 ((uint)0x00000001)
163
164
165
166#define SCC_GSMRH_IRP ((uint)0x00040000)
167#define SCC_GSMRH_GDE ((uint)0x00010000)
168#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
169#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
170#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
171#define SCC_GSMRH_REVD ((uint)0x00002000)
172#define SCC_GSMRH_TRX ((uint)0x00001000)
173#define SCC_GSMRH_TTX ((uint)0x00000800)
174#define SCC_GSMRH_CDP ((uint)0x00000400)
175#define SCC_GSMRH_CTSP ((uint)0x00000200)
176#define SCC_GSMRH_CDS ((uint)0x00000100)
177#define SCC_GSMRH_CTSS ((uint)0x00000080)
178#define SCC_GSMRH_TFL ((uint)0x00000040)
179#define SCC_GSMRH_RFW ((uint)0x00000020)
180#define SCC_GSMRH_TXSY ((uint)0x00000010)
181#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
182#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
183#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
184#define SCC_GSMRH_RTSM ((uint)0x00000002)
185#define SCC_GSMRH_RSYN ((uint)0x00000001)
186
187#define SCC_GSMRL_SIR ((uint)0x80000000)
188#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
189#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
190#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
191#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
192#define SCC_GSMRL_TCI ((uint)0x10000000)
193#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
194#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
195#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
196#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
197#define SCC_GSMRL_RINV ((uint)0x02000000)
198#define SCC_GSMRL_TINV ((uint)0x01000000)
199#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
200#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
201#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
202#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
203#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
204#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
205#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
206#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
207#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
208#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
209#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
210#define SCC_GSMRL_TEND ((uint)0x00040000)
211#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
212#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
213#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
214#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
215#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
216#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
217#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
218#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
219#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
220#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
221#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
222#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
223#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
224#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
225#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
226#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
227#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
228#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
229#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0)
230#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
231#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
232#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
233#define SCC_GSMRL_ENR ((uint)0x00000020)
234#define SCC_GSMRL_ENT ((uint)0x00000010)
235#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
236#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
237#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
238#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
239#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
240#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
241#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
242#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
243#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
244#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
245
246#define SCC_TODR_TOD ((ushort)0x8000)
247
248
249
250#define SCCM_TXE ((unsigned char)0x10)
251#define SCCM_BSY ((unsigned char)0x04)
252#define SCCM_TX ((unsigned char)0x02)
253#define SCCM_RX ((unsigned char)0x01)
254
255typedef struct scc_param {
256 ushort scc_rbase;
257 ushort scc_tbase;
258 u_char scc_rfcr;
259 u_char scc_tfcr;
260 ushort scc_mrblr;
261 uint scc_rstate;
262 uint scc_idp;
263 ushort scc_rbptr;
264 ushort scc_ibc;
265 uint scc_rxtmp;
266 uint scc_tstate;
267 uint scc_tdp;
268 ushort scc_tbptr;
269 ushort scc_tbc;
270 uint scc_txtmp;
271 uint scc_rcrc;
272 uint scc_tcrc;
273} sccp_t;
274
275
276
277typedef struct scc_enet {
278 sccp_t sen_genscc;
279 uint sen_cpres;
280 uint sen_cmask;
281 uint sen_crcec;
282 uint sen_alec;
283 uint sen_disfc;
284 ushort sen_pads;
285 ushort sen_retlim;
286 ushort sen_retcnt;
287 ushort sen_maxflr;
288 ushort sen_minflr;
289 ushort sen_maxd1;
290 ushort sen_maxd2;
291 ushort sen_maxd;
292 ushort sen_dmacnt;
293 ushort sen_maxb;
294 ushort sen_gaddr1;
295 ushort sen_gaddr2;
296 ushort sen_gaddr3;
297 ushort sen_gaddr4;
298 uint sen_tbuf0data0;
299 uint sen_tbuf0data1;
300 uint sen_tbuf0rba;
301 uint sen_tbuf0crc;
302 ushort sen_tbuf0bcnt;
303 ushort sen_paddrh;
304 ushort sen_paddrm;
305 ushort sen_paddrl;
306 ushort sen_pper;
307 ushort sen_rfbdptr;
308 ushort sen_tfbdptr;
309 ushort sen_tlbdptr;
310 uint sen_tbuf1data0;
311 uint sen_tbuf1data1;
312 uint sen_tbuf1rba;
313 uint sen_tbuf1crc;
314 ushort sen_tbuf1bcnt;
315 ushort sen_txlen;
316 ushort sen_iaddr1;
317 ushort sen_iaddr2;
318 ushort sen_iaddr3;
319 ushort sen_iaddr4;
320 ushort sen_boffcnt;
321
322
323
324
325 ushort sen_taddrh;
326 ushort sen_taddrm;
327 ushort sen_taddrl;
328} scc_enet_t;
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331
332
333#define SCCE_ENET_GRA ((ushort)0x0080)
334#define SCCE_ENET_TXE ((ushort)0x0010)
335#define SCCE_ENET_RXF ((ushort)0x0008)
336#define SCCE_ENET_BSY ((ushort)0x0004)
337#define SCCE_ENET_TXB ((ushort)0x0002)
338#define SCCE_ENET_RXB ((ushort)0x0001)
339
340
341
342#define SCC_PSMR_HBC ((ushort)0x8000)
343#define SCC_PSMR_FC ((ushort)0x4000)
344#define SCC_PSMR_RSH ((ushort)0x2000)
345#define SCC_PSMR_IAM ((ushort)0x1000)
346#define SCC_PSMR_ENCRC ((ushort)0x0800)
347#define SCC_PSMR_PRO ((ushort)0x0200)
348#define SCC_PSMR_BRO ((ushort)0x0100)
349#define SCC_PSMR_SBT ((ushort)0x0080)
350#define SCC_PSMR_LPB ((ushort)0x0040)
351#define SCC_PSMR_SIP ((ushort)0x0020)
352#define SCC_PSMR_LCW ((ushort)0x0010)
353#define SCC_PSMR_NIB22 ((ushort)0x000a)
354#define SCC_PSMR_FDE ((ushort)0x0001)
355
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357
358
359#define BD_ENET_RX_EMPTY ((ushort)0x8000)
360#define BD_ENET_RX_WRAP ((ushort)0x2000)
361#define BD_ENET_RX_INTR ((ushort)0x1000)
362#define BD_ENET_RX_LAST ((ushort)0x0800)
363#define BD_ENET_RX_FIRST ((ushort)0x0400)
364#define BD_ENET_RX_MISS ((ushort)0x0100)
365#define BD_ENET_RX_BC ((ushort)0x0080)
366#define BD_ENET_RX_MC ((ushort)0x0040)
367#define BD_ENET_RX_LG ((ushort)0x0020)
368#define BD_ENET_RX_NO ((ushort)0x0010)
369#define BD_ENET_RX_SH ((ushort)0x0008)
370#define BD_ENET_RX_CR ((ushort)0x0004)
371#define BD_ENET_RX_OV ((ushort)0x0002)
372#define BD_ENET_RX_CL ((ushort)0x0001)
373#define BD_ENET_RX_STATS ((ushort)0x01ff)
374
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376
377
378#define BD_ENET_TX_READY ((ushort)0x8000)
379#define BD_ENET_TX_PAD ((ushort)0x4000)
380#define BD_ENET_TX_WRAP ((ushort)0x2000)
381#define BD_ENET_TX_INTR ((ushort)0x1000)
382#define BD_ENET_TX_LAST ((ushort)0x0800)
383#define BD_ENET_TX_TC ((ushort)0x0400)
384#define BD_ENET_TX_DEF ((ushort)0x0200)
385#define BD_ENET_TX_HB ((ushort)0x0100)
386#define BD_ENET_TX_LC ((ushort)0x0080)
387#define BD_ENET_TX_RL ((ushort)0x0040)
388#define BD_ENET_TX_RCMASK ((ushort)0x003c)
389#define BD_ENET_TX_UN ((ushort)0x0002)
390#define BD_ENET_TX_CSL ((ushort)0x0001)
391#define BD_ENET_TX_STATS ((ushort)0x03ff)
392
393
394
395typedef struct scc_uart {
396 sccp_t scc_genscc;
397 uint scc_res1;
398 uint scc_res2;
399 ushort scc_maxidl;
400 ushort scc_idlc;
401 ushort scc_brkcr;
402 ushort scc_parec;
403 ushort scc_frmec;
404 ushort scc_nosec;
405 ushort scc_brkec;
406 ushort scc_brkln;
407 ushort scc_uaddr1;
408 ushort scc_uaddr2;
409 ushort scc_rtemp;
410 ushort scc_toseq;
411 ushort scc_char1;
412 ushort scc_char2;
413 ushort scc_char3;
414 ushort scc_char4;
415 ushort scc_char5;
416 ushort scc_char6;
417 ushort scc_char7;
418 ushort scc_char8;
419 ushort scc_rccm;
420 ushort scc_rccr;
421 ushort scc_rlbc;
422} scc_uart_t;
423
424
425
426#define UART_SCCM_GLR ((ushort)0x1000)
427#define UART_SCCM_GLT ((ushort)0x0800)
428#define UART_SCCM_AB ((ushort)0x0200)
429#define UART_SCCM_IDL ((ushort)0x0100)
430#define UART_SCCM_GRA ((ushort)0x0080)
431#define UART_SCCM_BRKE ((ushort)0x0040)
432#define UART_SCCM_BRKS ((ushort)0x0020)
433#define UART_SCCM_CCR ((ushort)0x0008)
434#define UART_SCCM_BSY ((ushort)0x0004)
435#define UART_SCCM_TX ((ushort)0x0002)
436#define UART_SCCM_RX ((ushort)0x0001)
437
438
439
440#define SCU_PSMR_FLC ((ushort)0x8000)
441#define SCU_PSMR_SL ((ushort)0x4000)
442#define SCU_PSMR_CL ((ushort)0x3000)
443#define SCU_PSMR_UM ((ushort)0x0c00)
444#define SCU_PSMR_FRZ ((ushort)0x0200)
445#define SCU_PSMR_RZS ((ushort)0x0100)
446#define SCU_PSMR_SYN ((ushort)0x0080)
447#define SCU_PSMR_DRT ((ushort)0x0040)
448#define SCU_PSMR_PEN ((ushort)0x0010)
449#define SCU_PSMR_RPM ((ushort)0x000c)
450#define SCU_PSMR_REVP ((ushort)0x0008)
451#define SCU_PSMR_TPM ((ushort)0x0003)
452#define SCU_PSMR_TEVP ((ushort)0x0003)
453
454
455
456typedef struct scc_trans {
457 sccp_t st_genscc;
458 uint st_cpres;
459 uint st_cmask;
460} scc_trans_t;
461
462#define BD_SCC_TX_LAST ((ushort)0x0800)
463
464
465
466#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
467#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
468#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
469#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
470#define FCC_GFMR_TCI ((uint)0x20000000)
471#define FCC_GFMR_TRX ((uint)0x10000000)
472#define FCC_GFMR_TTX ((uint)0x08000000)
473#define FCC_GFMR_TTX ((uint)0x08000000)
474#define FCC_GFMR_CDP ((uint)0x04000000)
475#define FCC_GFMR_CTSP ((uint)0x02000000)
476#define FCC_GFMR_CDS ((uint)0x01000000)
477#define FCC_GFMR_CTSS ((uint)0x00800000)
478#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
479#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
480#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
481#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
482#define FCC_GFMR_RTSM ((uint)0x00002000)
483#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
484#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
485#define FCC_GFMR_REVD ((uint)0x00000400)
486#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
487#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
488#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
489#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
490#define FCC_GFMR_ENR ((uint)0x00000020)
491#define FCC_GFMR_ENT ((uint)0x00000010)
492#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
493#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
494#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
495
496
497
498typedef struct fcc_param {
499 ushort fcc_riptr;
500 ushort fcc_tiptr;
501 ushort fcc_res1;
502 ushort fcc_mrblr;
503 uint fcc_rstate;
504 uint fcc_rbase;
505 ushort fcc_rbdstat;
506 ushort fcc_rbdlen;
507 uint fcc_rdptr;
508 uint fcc_tstate;
509 uint fcc_tbase;
510 ushort fcc_tbdstat;
511 ushort fcc_tbdlen;
512 uint fcc_tdptr;
513 uint fcc_rbptr;
514 uint fcc_tbptr;
515 uint fcc_rcrc;
516 uint fcc_res2;
517 uint fcc_tcrc;
518} fccp_t;
519
520
521
522
523typedef struct fcc_enet {
524 fccp_t fen_genfcc;
525 uint fen_statbuf;
526 uint fen_camptr;
527 uint fen_cmask;
528 uint fen_cpres;
529 uint fen_crcec;
530 uint fen_alec;
531 uint fen_disfc;
532 ushort fen_retlim;
533 ushort fen_retcnt;
534 ushort fen_pper;
535 ushort fen_boffcnt;
536 uint fen_gaddrh;
537 uint fen_gaddrl;
538 ushort fen_tfcstat;
539 ushort fen_tfclen;
540 uint fen_tfcptr;
541 ushort fen_mflr;
542 ushort fen_paddrh;
543 ushort fen_paddrm;
544 ushort fen_paddrl;
545 ushort fen_ibdcount;
546 ushort fen_ibdstart;
547 ushort fen_ibdend;
548 ushort fen_txlen;
549 uint fen_ibdbase[8];
550 uint fen_iaddrh;
551 uint fen_iaddrl;
552 ushort fen_minflr;
553 ushort fen_taddrh;
554 ushort fen_taddrm;
555 ushort fen_taddrl;
556 ushort fen_padptr;
557 ushort fen_cftype;
558 ushort fen_cfrange;
559 ushort fen_maxb;
560 ushort fen_maxd1;
561 ushort fen_maxd2;
562 ushort fen_maxd;
563 ushort fen_dmacnt;
564 uint fen_octc;
565 uint fen_colc;
566 uint fen_broc;
567 uint fen_mulc;
568 uint fen_uspc;
569 uint fen_frgc;
570 uint fen_ospc;
571 uint fen_jbrc;
572 uint fen_p64c;
573 uint fen_p65c;
574 uint fen_p128c;
575 uint fen_p256c;
576 uint fen_p512c;
577 uint fen_p1024c;
578 uint fen_cambuf;
579 ushort fen_rfthr;
580 ushort fen_rfcnt;
581} fcc_enet_t;
582
583
584
585#define FCC_ENET_GRA ((ushort)0x0080)
586#define FCC_ENET_RXC ((ushort)0x0040)
587#define FCC_ENET_TXC ((ushort)0x0020)
588#define FCC_ENET_TXE ((ushort)0x0010)
589#define FCC_ENET_RXF ((ushort)0x0008)
590#define FCC_ENET_BSY ((ushort)0x0004)
591#define FCC_ENET_TXB ((ushort)0x0002)
592#define FCC_ENET_RXB ((ushort)0x0001)
593
594
595
596#define FCC_PSMR_HBC ((uint)0x80000000)
597#define FCC_PSMR_FC ((uint)0x40000000)
598#define FCC_PSMR_SBT ((uint)0x20000000)
599#define FCC_PSMR_LPB ((uint)0x10000000)
600#define FCC_PSMR_LCW ((uint)0x08000000)
601#define FCC_PSMR_FDE ((uint)0x04000000)
602#define FCC_PSMR_MON ((uint)0x02000000)
603#define FCC_PSMR_PRO ((uint)0x00400000)
604#define FCC_PSMR_FCE ((uint)0x00200000)
605#define FCC_PSMR_RSH ((uint)0x00100000)
606#define FCC_PSMR_CAM ((uint)0x00000400)
607#define FCC_PSMR_BRO ((uint)0x00000200)
608#define FCC_PSMR_ENCRC ((uint)0x00000080)
609
610
611
612typedef struct iic {
613 ushort iic_rbase;
614 ushort iic_tbase;
615 u_char iic_rfcr;
616 u_char iic_tfcr;
617 ushort iic_mrblr;
618 uint iic_rstate;
619 uint iic_rdp;
620 ushort iic_rbptr;
621 ushort iic_rbc;
622 uint iic_rxtmp;
623 uint iic_tstate;
624 uint iic_tdp;
625 ushort iic_tbptr;
626 ushort iic_tbc;
627 uint iic_txtmp;
628} iic_t;
629
630
631
632typedef struct spi {
633 ushort spi_rbase;
634 ushort spi_tbase;
635 u_char spi_rfcr;
636 u_char spi_tfcr;
637 ushort spi_mrblr;
638 uint spi_rstate;
639 uint spi_rdp;
640 ushort spi_rbptr;
641 ushort spi_rbc;
642 uint spi_rxtmp;
643 uint spi_tstate;
644 uint spi_tdp;
645 ushort spi_tbptr;
646 ushort spi_tbc;
647 uint spi_txtmp;
648 uint spi_res;
649 uint spi_res1[4];
650} spi_t;
651
652
653
654#define SPMODE_LOOP ((ushort)0x4000)
655#define SPMODE_CI ((ushort)0x2000)
656#define SPMODE_CP ((ushort)0x1000)
657#define SPMODE_DIV16 ((ushort)0x0800)
658#define SPMODE_REV ((ushort)0x0400)
659#define SPMODE_MSTR ((ushort)0x0200)
660#define SPMODE_EN ((ushort)0x0100)
661#define SPMODE_LENMSK ((ushort)0x00f0)
662#define SPMODE_PMMSK ((ushort)0x000f)
663
664#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
665#define SPMODE_PM(x) ((x) &0xF)
666
667#define SPI_EB ((u_char)0x10)
668
669#define BD_IIC_START ((ushort)0x0400)
670
671
672
673
674#define CMXFCR_FC1 0x40000000
675#define CMXFCR_RF1CS_MSK 0x38000000
676#define CMXFCR_TF1CS_MSK 0x07000000
677#define CMXFCR_FC2 0x00400000
678#define CMXFCR_RF2CS_MSK 0x00380000
679#define CMXFCR_TF2CS_MSK 0x00070000
680#define CMXFCR_FC3 0x00004000
681#define CMXFCR_RF3CS_MSK 0x00003800
682#define CMXFCR_TF3CS_MSK 0x00000700
683
684#define CMXFCR_RF1CS_BRG5 0x00000000
685#define CMXFCR_RF1CS_BRG6 0x08000000
686#define CMXFCR_RF1CS_BRG7 0x10000000
687#define CMXFCR_RF1CS_BRG8 0x18000000
688#define CMXFCR_RF1CS_CLK9 0x20000000
689#define CMXFCR_RF1CS_CLK10 0x28000000
690#define CMXFCR_RF1CS_CLK11 0x30000000
691#define CMXFCR_RF1CS_CLK12 0x38000000
692
693#define CMXFCR_TF1CS_BRG5 0x00000000
694#define CMXFCR_TF1CS_BRG6 0x01000000
695#define CMXFCR_TF1CS_BRG7 0x02000000
696#define CMXFCR_TF1CS_BRG8 0x03000000
697#define CMXFCR_TF1CS_CLK9 0x04000000
698#define CMXFCR_TF1CS_CLK10 0x05000000
699#define CMXFCR_TF1CS_CLK11 0x06000000
700#define CMXFCR_TF1CS_CLK12 0x07000000
701
702#define CMXFCR_RF2CS_BRG5 0x00000000
703#define CMXFCR_RF2CS_BRG6 0x00080000
704#define CMXFCR_RF2CS_BRG7 0x00100000
705#define CMXFCR_RF2CS_BRG8 0x00180000
706#define CMXFCR_RF2CS_CLK13 0x00200000
707#define CMXFCR_RF2CS_CLK14 0x00280000
708#define CMXFCR_RF2CS_CLK15 0x00300000
709#define CMXFCR_RF2CS_CLK16 0x00380000
710
711#define CMXFCR_TF2CS_BRG5 0x00000000
712#define CMXFCR_TF2CS_BRG6 0x00010000
713#define CMXFCR_TF2CS_BRG7 0x00020000
714#define CMXFCR_TF2CS_BRG8 0x00030000
715#define CMXFCR_TF2CS_CLK13 0x00040000
716#define CMXFCR_TF2CS_CLK14 0x00050000
717#define CMXFCR_TF2CS_CLK15 0x00060000
718#define CMXFCR_TF2CS_CLK16 0x00070000
719
720#define CMXFCR_RF3CS_BRG5 0x00000000
721#define CMXFCR_RF3CS_BRG6 0x00000800
722#define CMXFCR_RF3CS_BRG7 0x00001000
723#define CMXFCR_RF3CS_BRG8 0x00001800
724#define CMXFCR_RF3CS_CLK13 0x00002000
725#define CMXFCR_RF3CS_CLK14 0x00002800
726#define CMXFCR_RF3CS_CLK15 0x00003000
727#define CMXFCR_RF3CS_CLK16 0x00003800
728
729#define CMXFCR_TF3CS_BRG5 0x00000000
730#define CMXFCR_TF3CS_BRG6 0x00000100
731#define CMXFCR_TF3CS_BRG7 0x00000200
732#define CMXFCR_TF3CS_BRG8 0x00000300
733#define CMXFCR_TF3CS_CLK13 0x00000400
734#define CMXFCR_TF3CS_CLK14 0x00000500
735#define CMXFCR_TF3CS_CLK15 0x00000600
736#define CMXFCR_TF3CS_CLK16 0x00000700
737
738
739
740
741#define CMXSCR_GR1 0x80000000
742#define CMXSCR_SC1 0x40000000
743#define CMXSCR_RS1CS_MSK 0x38000000
744#define CMXSCR_TS1CS_MSK 0x07000000
745#define CMXSCR_GR2 0x00800000
746#define CMXSCR_SC2 0x00400000
747#define CMXSCR_RS2CS_MSK 0x00380000
748#define CMXSCR_TS2CS_MSK 0x00070000
749#define CMXSCR_GR3 0x00008000
750#define CMXSCR_SC3 0x00004000
751#define CMXSCR_RS3CS_MSK 0x00003800
752#define CMXSCR_TS3CS_MSK 0x00000700
753#define CMXSCR_GR4 0x00000080
754#define CMXSCR_SC4 0x00000040
755#define CMXSCR_RS4CS_MSK 0x00000038
756#define CMXSCR_TS4CS_MSK 0x00000007
757
758#define CMXSCR_RS1CS_BRG1 0x00000000
759#define CMXSCR_RS1CS_BRG2 0x08000000
760#define CMXSCR_RS1CS_BRG3 0x10000000
761#define CMXSCR_RS1CS_BRG4 0x18000000
762#define CMXSCR_RS1CS_CLK11 0x20000000
763#define CMXSCR_RS1CS_CLK12 0x28000000
764#define CMXSCR_RS1CS_CLK3 0x30000000
765#define CMXSCR_RS1CS_CLK4 0x38000000
766
767#define CMXSCR_TS1CS_BRG1 0x00000000
768#define CMXSCR_TS1CS_BRG2 0x01000000
769#define CMXSCR_TS1CS_BRG3 0x02000000
770#define CMXSCR_TS1CS_BRG4 0x03000000
771#define CMXSCR_TS1CS_CLK11 0x04000000
772#define CMXSCR_TS1CS_CLK12 0x05000000
773#define CMXSCR_TS1CS_CLK3 0x06000000
774#define CMXSCR_TS1CS_CLK4 0x07000000
775
776#define CMXSCR_RS2CS_BRG1 0x00000000
777#define CMXSCR_RS2CS_BRG2 0x00080000
778#define CMXSCR_RS2CS_BRG3 0x00100000
779#define CMXSCR_RS2CS_BRG4 0x00180000
780#define CMXSCR_RS2CS_CLK11 0x00200000
781#define CMXSCR_RS2CS_CLK12 0x00280000
782#define CMXSCR_RS2CS_CLK3 0x00300000
783#define CMXSCR_RS2CS_CLK4 0x00380000
784
785#define CMXSCR_TS2CS_BRG1 0x00000000
786#define CMXSCR_TS2CS_BRG2 0x00010000
787#define CMXSCR_TS2CS_BRG3 0x00020000
788#define CMXSCR_TS2CS_BRG4 0x00030000
789#define CMXSCR_TS2CS_CLK11 0x00040000
790#define CMXSCR_TS2CS_CLK12 0x00050000
791#define CMXSCR_TS2CS_CLK3 0x00060000
792#define CMXSCR_TS2CS_CLK4 0x00070000
793
794#define CMXSCR_RS3CS_BRG1 0x00000000
795#define CMXSCR_RS3CS_BRG2 0x00000800
796#define CMXSCR_RS3CS_BRG3 0x00001000
797#define CMXSCR_RS3CS_BRG4 0x00001800
798#define CMXSCR_RS3CS_CLK5 0x00002000
799#define CMXSCR_RS3CS_CLK6 0x00002800
800#define CMXSCR_RS3CS_CLK7 0x00003000
801#define CMXSCR_RS3CS_CLK8 0x00003800
802
803#define CMXSCR_TS3CS_BRG1 0x00000000
804#define CMXSCR_TS3CS_BRG2 0x00000100
805#define CMXSCR_TS3CS_BRG3 0x00000200
806#define CMXSCR_TS3CS_BRG4 0x00000300
807#define CMXSCR_TS3CS_CLK5 0x00000400
808#define CMXSCR_TS3CS_CLK6 0x00000500
809#define CMXSCR_TS3CS_CLK7 0x00000600
810#define CMXSCR_TS3CS_CLK8 0x00000700
811
812#define CMXSCR_RS4CS_BRG1 0x00000000
813#define CMXSCR_RS4CS_BRG2 0x00000008
814#define CMXSCR_RS4CS_BRG3 0x00000010
815#define CMXSCR_RS4CS_BRG4 0x00000018
816#define CMXSCR_RS4CS_CLK5 0x00000020
817#define CMXSCR_RS4CS_CLK6 0x00000028
818#define CMXSCR_RS4CS_CLK7 0x00000030
819#define CMXSCR_RS4CS_CLK8 0x00000038
820
821#define CMXSCR_TS4CS_BRG1 0x00000000
822#define CMXSCR_TS4CS_BRG2 0x00000001
823#define CMXSCR_TS4CS_BRG3 0x00000002
824#define CMXSCR_TS4CS_BRG4 0x00000003
825#define CMXSCR_TS4CS_CLK5 0x00000004
826#define CMXSCR_TS4CS_CLK6 0x00000005
827#define CMXSCR_TS4CS_CLK7 0x00000006
828#define CMXSCR_TS4CS_CLK8 0x00000007
829
830#endif
831