LXR uboot/arch/x86/cpu/interrupts.c

   1/*
   2 * (C) Copyright 2008-2011
   3 * Graeme Russ, <graeme.russ@gmail.com>
   4 *
   5 * (C) Copyright 2002
   6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
   7 *
   8 * Portions of this file are derived from the Linux kernel source
   9 *  Copyright (C) 1991, 1992  Linus Torvalds
  10 *
  11 * See file CREDITS for list of people who contributed to this
  12 * project.
  13 *
  14 * This program is free software; you can redistribute it and/or
  15 * modify it under the terms of the GNU General Public License as
  16 * published by the Free Software Foundation; either version 2 of
  17 * the License, or (at your option) any later version.
  18 *
  19 * This program is distributed in the hope that it will be useful,
  20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22 * GNU General Public License for more details.
  23 *
  24 * You should have received a copy of the GNU General Public License
  25 * along with this program; if not, write to the Free Software
  26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27 * MA 02111-1307 USA
  28 */
  29
  30#include <common.h>
  31#include <asm/cache.h>
  32#include <asm/control_regs.h>
  33#include <asm/interrupt.h>
  34#include <asm/io.h>
  35#include <asm/processor-flags.h>
  36#include <linux/compiler.h>
  37#include <asm/msr.h>
  38#include <asm/u-boot-x86.h>
  39
  40#define DECLARE_INTERRUPT(x) \
  41        ".globl irq_"#x"\n" \
  42        ".hidden irq_"#x"\n" \
  43        ".type irq_"#x", @function\n" \
  44        "irq_"#x":\n" \
  45        "pushl $"#x"\n" \
  46        "jmp irq_common_entry\n"
  47
  48void dump_regs(struct irq_regs *regs)
  49{
  50        unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
  51        unsigned long d0, d1, d2, d3, d6, d7;
  52        unsigned long sp;
  53
  54        printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
  55                        (u16)regs->xcs, regs->eip, regs->eflags);
  56
  57        printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
  58                regs->eax, regs->ebx, regs->ecx, regs->edx);
  59        printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
  60                regs->esi, regs->edi, regs->ebp, regs->esp);
  61        printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
  62               (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
  63               (u16)regs->xgs, (u16)regs->xss);
  64
  65        cr0 = read_cr0();
  66        cr2 = read_cr2();
  67        cr3 = read_cr3();
  68        cr4 = read_cr4();
  69
  70        printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
  71                        cr0, cr2, cr3, cr4);
  72
  73        d0 = get_debugreg(0);
  74        d1 = get_debugreg(1);
  75        d2 = get_debugreg(2);
  76        d3 = get_debugreg(3);
  77
  78        printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
  79                        d0, d1, d2, d3);
  80
  81        d6 = get_debugreg(6);
  82        d7 = get_debugreg(7);
  83        printf("DR6: %08lx DR7: %08lx\n",
  84                        d6, d7);
  85
  86        printf("Stack:\n");
  87        sp = regs->esp;
  88
  89        sp += 64;
  90
  91        while (sp > (regs->esp - 16)) {
  92                if (sp == regs->esp)
  93                        printf("--->");
  94                else
  95                        printf("    ");
  96                printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
  97                sp -= 4;
  98        }
  99}
 100
 101struct idt_entry {
 102        u16     base_low;
 103        u16     selector;
 104        u8      res;
 105        u8      access;
 106        u16     base_high;
 107} __packed;
 108
 109struct desc_ptr {
 110        unsigned short size;
 111        unsigned long address;
 112        unsigned short segment;
 113} __packed;
 114
 115struct idt_entry idt[256] __aligned(16);
 116
 117struct desc_ptr idt_ptr;
 118
 119static inline void load_idt(const struct desc_ptr *dtr)
 120{
 121        asm volatile("cs lidt %0" : : "m" (*dtr));
 122}
 123
 124void set_vector(u8 intnum, void *routine)
 125{
 126        idt[intnum].base_high = (u16)((u32)(routine) >> 16);
 127        idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
 128}
 129
 130/*
 131 * Ideally these would be defined static to avoid a checkpatch warning, but
 132 * the compiler cannot see them in the inline asm and complains that they
 133 * aren't defined
 134 */
 135void irq_0(void);
 136void irq_1(void);
 137
 138int cpu_init_interrupts(void)
 139{
 140        int i;
 141
 142        int irq_entry_size = irq_1 - irq_0;
 143        void *irq_entry = (void *)irq_0;
 144
 145        /* Just in case... */
 146        disable_interrupts();
 147
 148        /* Setup the IDT */
 149        for (i = 0; i < 256; i++) {
 150                idt[i].access = 0x8e;
 151                idt[i].res = 0;
 152                idt[i].selector = 0x10;
 153                set_vector(i, irq_entry);
 154                irq_entry += irq_entry_size;
 155        }
 156
 157        idt_ptr.size = 256 * 8;
 158        idt_ptr.address = (unsigned long) idt;
 159        idt_ptr.segment = 0x18;
 160
 161        load_idt(&idt_ptr);
 162
 163        /* It is now safe to enable interrupts */
 164        enable_interrupts();
 165
 166        return 0;
 167}
 168
 169void __do_irq(int irq)
 170{
 171        printf("Unhandled IRQ : %d\n", irq);
 172}
 173void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
 174
 175void enable_interrupts(void)
 176{
 177        asm("sti\n");
 178}
 179
 180int disable_interrupts(void)
 181{
 182        long flags;
 183
 184        asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
 185
 186        return flags & X86_EFLAGS_IF;
 187}
 188
 189/* IRQ Low-Level Service Routine */
 190void irq_llsr(struct irq_regs *regs)
 191{
 192        /*
 193         * For detailed description of each exception, refer to:
 194         * Intel® 64 and IA-32 Architectures Software Developer's Manual
 195         * Volume 1: Basic Architecture
 196         * Order Number: 253665-029US, November 2008
 197         * Table 6-1. Exceptions and Interrupts
 198         */
 199        switch (regs->irq_id) {
 200        case 0x00:
 201                printf("Divide Error (Division by zero)\n");
 202                dump_regs(regs);
 203                hang();
 204                break;
 205        case 0x01:
 206                printf("Debug Interrupt (Single step)\n");
 207                dump_regs(regs);
 208                break;
 209        case 0x02:
 210                printf("NMI Interrupt\n");
 211                dump_regs(regs);
 212                break;
 213        case 0x03:
 214                printf("Breakpoint\n");
 215                dump_regs(regs);
 216                break;
 217        case 0x04:
 218                printf("Overflow\n");
 219                dump_regs(regs);
 220                hang();
 221                break;
 222        case 0x05:
 223                printf("BOUND Range Exceeded\n");
 224                dump_regs(regs);
 225                hang();
 226                break;
 227        case 0x06:
 228                printf("Invalid Opcode (UnDefined Opcode)\n");
 229                dump_regs(regs);
 230                hang();
 231                break;
 232        case 0x07:
 233                printf("Device Not Available (No Math Coprocessor)\n");
 234                dump_regs(regs);
 235                hang();
 236                break;
 237        case 0x08:
 238                printf("Double fault\n");
 239                dump_regs(regs);
 240                hang();
 241                break;
 242        case 0x09:
 243                printf("Co-processor segment overrun\n");
 244                dump_regs(regs);
 245                hang();
 246                break;
 247        case 0x0a:
 248                printf("Invalid TSS\n");
 249                dump_regs(regs);
 250                break;
 251        case 0x0b:
 252                printf("Segment Not Present\n");
 253                dump_regs(regs);
 254                hang();
 255                break;
 256        case 0x0c:
 257                printf("Stack Segment Fault\n");
 258                dump_regs(regs);
 259                hang();
 260                break;
 261        case 0x0d:
 262                printf("General Protection\n");
 263                dump_regs(regs);
 264                break;
 265        case 0x0e:
 266                printf("Page fault\n");
 267                dump_regs(regs);
 268                hang();
 269                break;
 270        case 0x0f:
 271                printf("Floating-Point Error (Math Fault)\n");
 272                dump_regs(regs);
 273                break;
 274        case 0x10:
 275                printf("Alignment check\n");
 276                dump_regs(regs);
 277                break;
 278        case 0x11:
 279                printf("Machine Check\n");
 280                dump_regs(regs);
 281                break;
 282        case 0x12:
 283                printf("SIMD Floating-Point Exception\n");
 284                dump_regs(regs);
 285                break;
 286        case 0x13:
 287        case 0x14:
 288        case 0x15:
 289        case 0x16:
 290        case 0x17:
 291        case 0x18:
 292        case 0x19:
 293        case 0x1a:
 294        case 0x1b:
 295        case 0x1c:
 296        case 0x1d:
 297        case 0x1e:
 298        case 0x1f:
 299                printf("Reserved Exception\n");
 300                dump_regs(regs);
 301                break;
 302
 303        default:
 304                /* Hardware or User IRQ */
 305                do_irq(regs->irq_id);
 306        }
 307}
 308
 309/*
 310 * OK - This looks really horrible, but it serves a purpose - It helps create
 311 * fully relocatable code.
 312 *  - The call to irq_llsr will be a relative jump
 313 *  - The IRQ entries will be guaranteed to be in order
 314 *  Interrupt entries are now very small (a push and a jump) but they are
 315 *  now slower (all registers pushed on stack which provides complete
 316 *  crash dumps in the low level handlers
 317 *
 318 * Interrupt Entry Point:
 319 *  - Interrupt has caused eflags, CS and EIP to be pushed
 320 *  - Interrupt Vector Handler has pushed orig_eax
 321 *  - pt_regs.esp needs to be adjusted by 40 bytes:
 322 *      12 bytes pushed by CPU (EFLAGSF, CS, EIP)
 323 *      4 bytes pushed by vector handler (irq_id)
 324 *      24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
 325 *      NOTE: Only longs are pushed on/popped off the stack!
 326 */
 327asm(".globl irq_common_entry\n" \
 328        ".hidden irq_common_entry\n" \
 329        ".type irq_common_entry, @function\n" \
 330        "irq_common_entry:\n" \
 331        "cld\n" \
 332        "pushl %ss\n" \
 333        "pushl %gs\n" \
 334        "pushl %fs\n" \
 335        "pushl %es\n" \
 336        "pushl %ds\n" \
 337        "pushl %eax\n" \
 338        "movl  %esp, %eax\n" \
 339        "addl  $40, %eax\n" \
 340        "pushl %eax\n" \
 341        "pushl %ebp\n" \
 342        "pushl %edi\n" \
 343        "pushl %esi\n" \
 344        "pushl %edx\n" \
 345        "pushl %ecx\n" \
 346        "pushl %ebx\n" \
 347        "mov   %esp, %eax\n" \
 348        "call irq_llsr\n" \
 349        "popl %ebx\n" \
 350        "popl %ecx\n" \
 351        "popl %edx\n" \
 352        "popl %esi\n" \
 353        "popl %edi\n" \
 354        "popl %ebp\n" \
 355        "popl %eax\n" \
 356        "popl %eax\n" \
 357        "popl %ds\n" \
 358        "popl %es\n" \
 359        "popl %fs\n" \
 360        "popl %gs\n" \
 361        "popl %ss\n" \
 362        "add  $4, %esp\n" \
 363        "iret\n" \
 364        DECLARE_INTERRUPT(0) \
 365        DECLARE_INTERRUPT(1) \
 366        DECLARE_INTERRUPT(2) \
 367        DECLARE_INTERRUPT(3) \
 368        DECLARE_INTERRUPT(4) \
 369        DECLARE_INTERRUPT(5) \
 370        DECLARE_INTERRUPT(6) \
 371        DECLARE_INTERRUPT(7) \
 372        DECLARE_INTERRUPT(8) \
 373        DECLARE_INTERRUPT(9) \
 374        DECLARE_INTERRUPT(10) \
 375        DECLARE_INTERRUPT(11) \
 376        DECLARE_INTERRUPT(12) \
 377        DECLARE_INTERRUPT(13) \
 378        DECLARE_INTERRUPT(14) \
 379        DECLARE_INTERRUPT(15) \
 380        DECLARE_INTERRUPT(16) \
 381        DECLARE_INTERRUPT(17) \
 382        DECLARE_INTERRUPT(18) \
 383        DECLARE_INTERRUPT(19) \
 384        DECLARE_INTERRUPT(20) \
 385        DECLARE_INTERRUPT(21) \
 386        DECLARE_INTERRUPT(22) \
 387        DECLARE_INTERRUPT(23) \
 388        DECLARE_INTERRUPT(24) \
 389        DECLARE_INTERRUPT(25) \
 390        DECLARE_INTERRUPT(26) \
 391        DECLARE_INTERRUPT(27) \
 392        DECLARE_INTERRUPT(28) \
 393        DECLARE_INTERRUPT(29) \
 394        DECLARE_INTERRUPT(30) \
 395        DECLARE_INTERRUPT(31) \
 396        DECLARE_INTERRUPT(32) \
 397        DECLARE_INTERRUPT(33) \
 398        DECLARE_INTERRUPT(34) \
 399        DECLARE_INTERRUPT(35) \
 400        DECLARE_INTERRUPT(36) \
 401        DECLARE_INTERRUPT(37) \
 402        DECLARE_INTERRUPT(38) \
 403        DECLARE_INTERRUPT(39) \
 404        DECLARE_INTERRUPT(40) \
 405        DECLARE_INTERRUPT(41) \
 406        DECLARE_INTERRUPT(42) \
 407        DECLARE_INTERRUPT(43) \
 408        DECLARE_INTERRUPT(44) \
 409        DECLARE_INTERRUPT(45) \
 410        DECLARE_INTERRUPT(46) \
 411        DECLARE_INTERRUPT(47) \
 412        DECLARE_INTERRUPT(48) \
 413        DECLARE_INTERRUPT(49) \
 414        DECLARE_INTERRUPT(50) \
 415        DECLARE_INTERRUPT(51) \
 416        DECLARE_INTERRUPT(52) \
 417        DECLARE_INTERRUPT(53) \
 418        DECLARE_INTERRUPT(54) \
 419        DECLARE_INTERRUPT(55) \
 420        DECLARE_INTERRUPT(56) \
 421        DECLARE_INTERRUPT(57) \
 422        DECLARE_INTERRUPT(58) \
 423        DECLARE_INTERRUPT(59) \
 424        DECLARE_INTERRUPT(60) \
 425        DECLARE_INTERRUPT(61) \
 426        DECLARE_INTERRUPT(62) \
 427        DECLARE_INTERRUPT(63) \
 428        DECLARE_INTERRUPT(64) \
 429        DECLARE_INTERRUPT(65) \
 430        DECLARE_INTERRUPT(66) \
 431        DECLARE_INTERRUPT(67) \
 432        DECLARE_INTERRUPT(68) \
 433        DECLARE_INTERRUPT(69) \
 434        DECLARE_INTERRUPT(70) \
 435        DECLARE_INTERRUPT(71) \
 436        DECLARE_INTERRUPT(72) \
 437        DECLARE_INTERRUPT(73) \
 438        DECLARE_INTERRUPT(74) \
 439        DECLARE_INTERRUPT(75) \
 440        DECLARE_INTERRUPT(76) \
 441        DECLARE_INTERRUPT(77) \
 442        DECLARE_INTERRUPT(78) \
 443        DECLARE_INTERRUPT(79) \
 444        DECLARE_INTERRUPT(80) \
 445        DECLARE_INTERRUPT(81) \
 446        DECLARE_INTERRUPT(82) \
 447        DECLARE_INTERRUPT(83) \
 448        DECLARE_INTERRUPT(84) \
 449        DECLARE_INTERRUPT(85) \
 450        DECLARE_INTERRUPT(86) \
 451        DECLARE_INTERRUPT(87) \
 452        DECLARE_INTERRUPT(88) \
 453        DECLARE_INTERRUPT(89) \
 454        DECLARE_INTERRUPT(90) \
 455        DECLARE_INTERRUPT(91) \
 456        DECLARE_INTERRUPT(92) \
 457        DECLARE_INTERRUPT(93) \
 458        DECLARE_INTERRUPT(94) \
 459        DECLARE_INTERRUPT(95) \
 460        DECLARE_INTERRUPT(97) \
 461        DECLARE_INTERRUPT(96) \
 462        DECLARE_INTERRUPT(98) \
 463        DECLARE_INTERRUPT(99) \
 464        DECLARE_INTERRUPT(100) \
 465        DECLARE_INTERRUPT(101) \
 466        DECLARE_INTERRUPT(102) \
 467        DECLARE_INTERRUPT(103) \
 468        DECLARE_INTERRUPT(104) \
 469        DECLARE_INTERRUPT(105) \
 470        DECLARE_INTERRUPT(106) \
 471        DECLARE_INTERRUPT(107) \
 472        DECLARE_INTERRUPT(108) \
 473        DECLARE_INTERRUPT(109) \
 474        DECLARE_INTERRUPT(110) \
 475        DECLARE_INTERRUPT(111) \
 476        DECLARE_INTERRUPT(112) \
 477        DECLARE_INTERRUPT(113) \
 478        DECLARE_INTERRUPT(114) \
 479        DECLARE_INTERRUPT(115) \
 480        DECLARE_INTERRUPT(116) \
 481        DECLARE_INTERRUPT(117) \
 482        DECLARE_INTERRUPT(118) \
 483        DECLARE_INTERRUPT(119) \
 484        DECLARE_INTERRUPT(120) \
 485        DECLARE_INTERRUPT(121) \
 486        DECLARE_INTERRUPT(122) \
 487        DECLARE_INTERRUPT(123) \
 488        DECLARE_INTERRUPT(124) \
 489        DECLARE_INTERRUPT(125) \
 490        DECLARE_INTERRUPT(126) \
 491        DECLARE_INTERRUPT(127) \
 492        DECLARE_INTERRUPT(128) \
 493        DECLARE_INTERRUPT(129) \
 494        DECLARE_INTERRUPT(130) \
 495        DECLARE_INTERRUPT(131) \
 496        DECLARE_INTERRUPT(132) \
 497        DECLARE_INTERRUPT(133) \
 498        DECLARE_INTERRUPT(134) \
 499        DECLARE_INTERRUPT(135) \
 500        DECLARE_INTERRUPT(136) \
 501        DECLARE_INTERRUPT(137) \
 502        DECLARE_INTERRUPT(138) \
 503        DECLARE_INTERRUPT(139) \
 504        DECLARE_INTERRUPT(140) \
 505        DECLARE_INTERRUPT(141) \
 506        DECLARE_INTERRUPT(142) \
 507        DECLARE_INTERRUPT(143) \
 508        DECLARE_INTERRUPT(144) \
 509        DECLARE_INTERRUPT(145) \
 510        DECLARE_INTERRUPT(146) \
 511        DECLARE_INTERRUPT(147) \
 512        DECLARE_INTERRUPT(148) \
 513        DECLARE_INTERRUPT(149) \
 514        DECLARE_INTERRUPT(150) \
 515        DECLARE_INTERRUPT(151) \
 516        DECLARE_INTERRUPT(152) \
 517        DECLARE_INTERRUPT(153) \
 518        DECLARE_INTERRUPT(154) \
 519        DECLARE_INTERRUPT(155) \
 520        DECLARE_INTERRUPT(156) \
 521        DECLARE_INTERRUPT(157) \
 522        DECLARE_INTERRUPT(158) \
 523        DECLARE_INTERRUPT(159) \
 524        DECLARE_INTERRUPT(160) \
 525        DECLARE_INTERRUPT(161) \
 526        DECLARE_INTERRUPT(162) \
 527        DECLARE_INTERRUPT(163) \
 528        DECLARE_INTERRUPT(164) \
 529        DECLARE_INTERRUPT(165) \
 530        DECLARE_INTERRUPT(166) \
 531        DECLARE_INTERRUPT(167) \
 532        DECLARE_INTERRUPT(168) \
 533        DECLARE_INTERRUPT(169) \
 534        DECLARE_INTERRUPT(170) \
 535        DECLARE_INTERRUPT(171) \
 536        DECLARE_INTERRUPT(172) \
 537        DECLARE_INTERRUPT(173) \
 538        DECLARE_INTERRUPT(174) \
 539        DECLARE_INTERRUPT(175) \
 540        DECLARE_INTERRUPT(176) \
 541        DECLARE_INTERRUPT(177) \
 542        DECLARE_INTERRUPT(178) \
 543        DECLARE_INTERRUPT(179) \
 544        DECLARE_INTERRUPT(180) \
 545        DECLARE_INTERRUPT(181) \
 546        DECLARE_INTERRUPT(182) \
 547        DECLARE_INTERRUPT(183) \
 548        DECLARE_INTERRUPT(184) \
 549        DECLARE_INTERRUPT(185) \
 550        DECLARE_INTERRUPT(186) \
 551        DECLARE_INTERRUPT(187) \
 552        DECLARE_INTERRUPT(188) \
 553        DECLARE_INTERRUPT(189) \
 554        DECLARE_INTERRUPT(190) \
 555        DECLARE_INTERRUPT(191) \
 556        DECLARE_INTERRUPT(192) \
 557        DECLARE_INTERRUPT(193) \
 558        DECLARE_INTERRUPT(194) \
 559        DECLARE_INTERRUPT(195) \
 560        DECLARE_INTERRUPT(196) \
 561        DECLARE_INTERRUPT(197) \
 562        DECLARE_INTERRUPT(198) \
 563        DECLARE_INTERRUPT(199) \
 564        DECLARE_INTERRUPT(200) \
 565        DECLARE_INTERRUPT(201) \
 566        DECLARE_INTERRUPT(202) \
 567        DECLARE_INTERRUPT(203) \
 568        DECLARE_INTERRUPT(204) \
 569        DECLARE_INTERRUPT(205) \
 570        DECLARE_INTERRUPT(206) \
 571        DECLARE_INTERRUPT(207) \
 572        DECLARE_INTERRUPT(208) \
 573        DECLARE_INTERRUPT(209) \
 574        DECLARE_INTERRUPT(210) \
 575        DECLARE_INTERRUPT(211) \
 576        DECLARE_INTERRUPT(212) \
 577        DECLARE_INTERRUPT(213) \
 578        DECLARE_INTERRUPT(214) \
 579        DECLARE_INTERRUPT(215) \
 580        DECLARE_INTERRUPT(216) \
 581        DECLARE_INTERRUPT(217) \
 582        DECLARE_INTERRUPT(218) \
 583        DECLARE_INTERRUPT(219) \
 584        DECLARE_INTERRUPT(220) \
 585        DECLARE_INTERRUPT(221) \
 586        DECLARE_INTERRUPT(222) \
 587        DECLARE_INTERRUPT(223) \
 588        DECLARE_INTERRUPT(224) \
 589        DECLARE_INTERRUPT(225) \
 590        DECLARE_INTERRUPT(226) \
 591        DECLARE_INTERRUPT(227) \
 592        DECLARE_INTERRUPT(228) \
 593        DECLARE_INTERRUPT(229) \
 594        DECLARE_INTERRUPT(230) \
 595        DECLARE_INTERRUPT(231) \
 596        DECLARE_INTERRUPT(232) \
 597        DECLARE_INTERRUPT(233) \
 598        DECLARE_INTERRUPT(234) \
 599        DECLARE_INTERRUPT(235) \
 600        DECLARE_INTERRUPT(236) \
 601        DECLARE_INTERRUPT(237) \
 602        DECLARE_INTERRUPT(238) \
 603        DECLARE_INTERRUPT(239) \
 604        DECLARE_INTERRUPT(240) \
 605        DECLARE_INTERRUPT(241) \
 606        DECLARE_INTERRUPT(242) \
 607        DECLARE_INTERRUPT(243) \
 608        DECLARE_INTERRUPT(244) \
 609        DECLARE_INTERRUPT(245) \
 610        DECLARE_INTERRUPT(246) \
 611        DECLARE_INTERRUPT(247) \
 612        DECLARE_INTERRUPT(248) \
 613        DECLARE_INTERRUPT(249) \
 614        DECLARE_INTERRUPT(250) \
 615        DECLARE_INTERRUPT(251) \
 616        DECLARE_INTERRUPT(252) \
 617        DECLARE_INTERRUPT(253) \
 618        DECLARE_INTERRUPT(254) \
 619        DECLARE_INTERRUPT(255));
 620
 621#if defined(CONFIG_INTEL_CORE_ARCH)
 622/*
 623 * Get the number of CPU time counter ticks since it was read first time after
 624 * restart. This yields a free running counter guaranteed to take almost 6
 625 * years to wrap around even at 100GHz clock rate.
 626 */
 627u64 get_ticks(void)
 628{
 629        u64 now_tick = rdtsc();
 630
 631        if (!gd->arch.tsc_base)
 632                gd->arch.tsc_base = now_tick;
 633
 634        return now_tick - gd->arch.tsc_base;
 635}
 636
 637#define PLATFORM_INFO_MSR 0xce
 638
 639unsigned long get_tbclk(void)
 640{
 641        u32 ratio;
 642        u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
 643
 644        ratio = (platform_info >> 8) & 0xff;
 645        return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */
 646}
 647#endif
 648