LXR uboot/board/freescale/b4860qds/ddr.c

   1/*
   2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License
   6 * Version 2 or later as published by the Free Software Foundation.
   7 */
   8
   9#include <common.h>
  10#include <i2c.h>
  11#include <hwconfig.h>
  12#include <asm/mmu.h>
  13#include <asm/fsl_ddr_sdram.h>
  14#include <asm/fsl_ddr_dimm_params.h>
  15#include <asm/fsl_law.h>
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19dimm_params_t ddr_raw_timing = {
  20        .n_ranks = 2,
  21        .rank_density = 2147483648u,
  22        .capacity = 4294967296u,
  23        .primary_sdram_width = 64,
  24        .ec_sdram_width = 8,
  25        .registered_dimm = 0,
  26        .mirrored_dimm = 1,
  27        .n_row_addr = 15,
  28        .n_col_addr = 10,
  29        .n_banks_per_sdram_device = 8,
  30        .edc_config = 2,        /* ECC */
  31        .burst_lengths_bitmask = 0x0c,
  32
  33        .tCKmin_X_ps = 1071,
  34        .caslat_X = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
  35        .tAA_ps = 13910,
  36        .tWR_ps = 15000,
  37        .tRCD_ps = 13910,
  38        .tRRD_ps = 6000,
  39        .tRP_ps = 13910,
  40        .tRAS_ps = 34000,
  41        .tRC_ps = 48910,
  42        .tRFC_ps = 260000,
  43        .tWTR_ps = 7500,
  44        .tRTP_ps = 7500,
  45        .refresh_rate_ps = 7800000,
  46        .tFAW_ps = 35000,
  47};
  48
  49int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  50                unsigned int controller_number,
  51                unsigned int dimm_number)
  52{
  53        const char dimm_model[] = "RAW timing DDR";
  54
  55        if ((controller_number == 0) && (dimm_number == 0)) {
  56                memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  57                memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  58                memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  59        }
  60
  61        return 0;
  62}
  63
  64struct board_specific_parameters {
  65        u32 n_ranks;
  66        u32 datarate_mhz_high;
  67        u32 clk_adjust;
  68        u32 wrlvl_start;
  69        u32 wrlvl_ctl_2;
  70        u32 wrlvl_ctl_3;
  71        u32 cpo;
  72        u32 write_data_delay;
  73        u32 force_2T;
  74};
  75
  76/*
  77 * This table contains all valid speeds we want to override with board
  78 * specific parameters. datarate_mhz_high values need to be in ascending order
  79 * for each n_ranks group.
  80 */
  81static const struct board_specific_parameters udimm0[] = {
  82        /*
  83         * memory controller 0
  84         *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
  85         * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
  86         */
  87        {2,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
  88        {2,  1666,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
  89        {2,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
  90        {1,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
  91        {1,  1700,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
  92        {1,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
  93        {}
  94};
  95
  96static const struct board_specific_parameters *udimms[] = {
  97        udimm0,
  98};
  99
 100void fsl_ddr_board_options(memctl_options_t *popts,
 101                                dimm_params_t *pdimm,
 102                                unsigned int ctrl_num)
 103{
 104        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 105        ulong ddr_freq;
 106
 107        if (ctrl_num > 2) {
 108                printf("Not supported controller number %d\n", ctrl_num);
 109                return;
 110        }
 111        if (!pdimm->n_ranks)
 112                return;
 113
 114        pbsp = udimms[0];
 115
 116
 117        /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 118         * freqency and n_banks specified in board_specific_parameters table.
 119         */
 120        ddr_freq = get_ddr_freq(0) / 1000000;
 121        while (pbsp->datarate_mhz_high) {
 122                if (pbsp->n_ranks == pdimm->n_ranks) {
 123                        if (ddr_freq <= pbsp->datarate_mhz_high) {
 124                                popts->cpo_override = pbsp->cpo;
 125                                popts->write_data_delay =
 126                                        pbsp->write_data_delay;
 127                                popts->clk_adjust = pbsp->clk_adjust;
 128                                popts->wrlvl_start = pbsp->wrlvl_start;
 129                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 130                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
 131                                popts->twoT_en = pbsp->force_2T;
 132                                goto found;
 133                        }
 134                        pbsp_highest = pbsp;
 135                }
 136                pbsp++;
 137        }
 138
 139        if (pbsp_highest) {
 140                printf("Error: board specific timing not found "
 141                        "for data rate %lu MT/s\n"
 142                        "Trying to use the highest speed (%u) parameters\n",
 143                        ddr_freq, pbsp_highest->datarate_mhz_high);
 144                popts->cpo_override = pbsp_highest->cpo;
 145                popts->write_data_delay = pbsp_highest->write_data_delay;
 146                popts->clk_adjust = pbsp_highest->clk_adjust;
 147                popts->wrlvl_start = pbsp_highest->wrlvl_start;
 148                popts->twoT_en = pbsp_highest->force_2T;
 149        } else {
 150                panic("DIMM is not supported by this board");
 151        }
 152found:
 153        /*
 154         * Factors to consider for half-strength driver enable:
 155         *      - number of DIMMs installed
 156         */
 157        popts->half_strength_driver_enable = 0;
 158        /*
 159         * Write leveling override
 160         */
 161        popts->wrlvl_override = 1;
 162        popts->wrlvl_sample = 0xf;
 163
 164        /*
 165         * Rtt and Rtt_WR override
 166         */
 167        popts->rtt_override = 0;
 168
 169        /* Enable ZQ calibration */
 170        popts->zq_en = 1;
 171
 172        /* DHC_EN =1, ODT = 75 Ohm */
 173        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 174        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 175}
 176
 177phys_size_t initdram(int board_type)
 178{
 179        phys_size_t dram_size;
 180
 181        puts("Initializing....using SPD\n");
 182
 183        dram_size = fsl_ddr_sdram();
 184
 185        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 186        dram_size *= 0x100000;
 187
 188        puts("    DDR: ");
 189        return dram_size;
 190}
 191