LXR uboot/board/freescale/mpc8541cds/mpc8541cds.c

   1/*
   2 * Copyright 2004, 2011 Freescale Semiconductor.
   3 *
   4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#include <common.h>
  26#include <pci.h>
  27#include <asm/processor.h>
  28#include <asm/mmu.h>
  29#include <asm/immap_85xx.h>
  30#include <asm/fsl_ddr_sdram.h>
  31#include <ioports.h>
  32#include <spd_sdram.h>
  33#include <libfdt.h>
  34#include <fdt_support.h>
  35
  36#include "../common/cadmus.h"
  37#include "../common/eeprom.h"
  38#include "../common/via.h"
  39
  40#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  41extern void ddr_enable_ecc(unsigned int dram_size);
  42#endif
  43
  44void local_bus_init(void);
  45
  46/*
  47 * I/O Port configuration table
  48 *
  49 * if conf is 1, then that port pin will be configured at boot time
  50 * according to the five values podr/pdir/ppar/psor/pdat for that entry
  51 */
  52
  53const iop_conf_t iop_conf_tab[4][32] = {
  54
  55    /* Port A configuration */
  56    {   /*            conf ppar psor pdir podr pdat */
  57        /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
  58        /* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
  59        /* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
  60        /* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
  61        /* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
  62        /* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
  63        /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  64        /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  65        /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  66        /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  67        /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
  68        /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
  69        /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
  70        /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
  71        /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
  72        /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
  73        /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
  74        /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
  75        /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  76        /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  77        /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  78        /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  79        /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  80        /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  81        /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  82        /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  83        /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  84        /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  85        /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  86        /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  87        /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
  88        /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  89    },
  90
  91    /* Port B configuration */
  92    {   /*            conf ppar psor pdir podr pdat */
  93        /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  94        /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  95        /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  96        /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  97        /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  98        /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  99        /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
 100        /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
 101        /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
 102        /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
 103        /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
 104        /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 105        /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 106        /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 107        /* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
 108        /* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
 109        /* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
 110        /* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
 111        /* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
 112        /* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
 113        /* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 114        /* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 115        /* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 116        /* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 117        /* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 118        /* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 119        /* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 120        /* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 121        /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 122        /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 123        /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 124        /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 125    },
 126
 127    /* Port C */
 128    {   /*            conf ppar psor pdir podr pdat */
 129        /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 130        /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 131        /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 132        /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 133        /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 134        /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 135        /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 136        /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 137        /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 138        /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 139        /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 140        /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 141        /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 142        /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 143        /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 144        /* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 145        /* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
 146        /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 147        /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 148        /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 149        /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 150        /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
 151        /* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 152        /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 153        /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 154        /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 155        /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 156        /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 157        /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 158        /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 159        /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 160        /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 161    },
 162
 163    /* Port D */
 164    {   /*            conf ppar psor pdir podr pdat */
 165        /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 166        /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 167        /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
 168        /* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
 169        /* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
 170        /* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
 171        /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 172        /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 173        /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 174        /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 175        /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 176        /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 177        /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 178        /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 179        /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 180        /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 181        /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 182        /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 183        /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 184        /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 185        /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 186        /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 187        /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 188        /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 189        /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 190        /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 191        /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 192        /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 193        /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 194        /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 195        /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 196        /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 197    }
 198};
 199
 200int checkboard (void)
 201{
 202        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 203        char buf[32];
 204
 205        /* PCI slot in USER bits CSR[6:7] by convention. */
 206        uint pci_slot = get_pci_slot ();
 207
 208        uint pci_dual = get_pci_dual ();        /* PCI DUAL in CM_PCI[3] */
 209        uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
 210        uint pci1_clk_sel = gur->porpllsr & 0x8000;     /* PORPLLSR[16] */
 211        uint pci2_clk_sel = gur->porpllsr & 0x4000;     /* PORPLLSR[17] */
 212
 213        uint pci1_speed = get_clock_freq ();    /* PCI PSPEED in [4:5] */
 214
 215        uint cpu_board_rev = get_cpu_board_revision ();
 216
 217        printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
 218                get_board_version (), pci_slot);
 219
 220        printf ("CPU Board Revision %d.%d (0x%04x)\n",
 221                MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
 222                MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
 223
 224        printf("PCI1: %d bit, %s MHz, %s\n",
 225                (pci1_32) ? 32 : 64,
 226                strmhz(buf, pci1_speed),
 227                pci1_clk_sel ? "sync" : "async");
 228
 229        if (pci_dual) {
 230                printf("PCI2: 32 bit, 66 MHz, %s\n",
 231                        pci2_clk_sel ? "sync" : "async");
 232        } else {
 233                printf("PCI2: disabled\n");
 234        }
 235
 236        /*
 237         * Initialize local bus.
 238         */
 239        local_bus_init ();
 240
 241        return 0;
 242}
 243
 244/*
 245 * Initialize Local Bus
 246 */
 247void
 248local_bus_init(void)
 249{
 250        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 251        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 252
 253        uint clkdiv;
 254        uint lbc_hz;
 255        sys_info_t sysinfo;
 256        uint temp_lbcdll;
 257
 258        /*
 259         * Errata LBC11.
 260         * Fix Local Bus clock glitch when DLL is enabled.
 261         *
 262         * If localbus freq is < 66MHz, DLL bypass mode must be used.
 263         * If localbus freq is > 133MHz, DLL can be safely enabled.
 264         * Between 66 and 133, the DLL is enabled with an override workaround.
 265         */
 266
 267        get_sys_info(&sysinfo);
 268        clkdiv = lbc->lcrr & LCRR_CLKDIV;
 269        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 270
 271        if (lbc_hz < 66) {
 272                lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
 273
 274        } else if (lbc_hz >= 133) {
 275                lbc->lcrr &= (~LCRR_DBYP);              /* DLL Enabled */
 276
 277        } else {
 278                lbc->lcrr &= (~LCRR_DBYP);      /* DLL Enabled */
 279                udelay(200);
 280
 281                /*
 282                 * Sample LBC DLL ctrl reg, upshift it to set the
 283                 * override bits.
 284                 */
 285                temp_lbcdll = gur->lbcdllcr;
 286                gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 287                asm("sync;isync;msync");
 288        }
 289}
 290
 291/*
 292 * Initialize SDRAM memory on the Local Bus.
 293 */
 294void lbc_sdram_init(void)
 295{
 296#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 297
 298        uint idx;
 299        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 300        uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 301        uint cpu_board_rev;
 302        uint lsdmr_common;
 303
 304        puts("LBC SDRAM: ");
 305        print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
 306                   "\n       ");
 307
 308        /*
 309         * Setup SDRAM Base and Option Registers
 310         */
 311        set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
 312        set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 313        lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 314        asm("msync");
 315
 316        lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 317        lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 318        asm("msync");
 319
 320        /*
 321         * Determine which address lines to use baed on CPU board rev.
 322         */
 323        cpu_board_rev = get_cpu_board_revision();
 324        lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 325        if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
 326                lsdmr_common |= LSDMR_BSMA1617;
 327        } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
 328                lsdmr_common |= LSDMR_BSMA1516;
 329        } else {
 330                /*
 331                 * Assume something unable to identify itself is
 332                 * really old, and likely has lines 16/17 mapped.
 333                 */
 334                lsdmr_common |= LSDMR_BSMA1617;
 335        }
 336
 337        /*
 338         * Issue PRECHARGE ALL command.
 339         */
 340        lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 341        asm("sync;msync");
 342        *sdram_addr = 0xff;
 343        ppcDcbf((unsigned long) sdram_addr);
 344        udelay(100);
 345
 346        /*
 347         * Issue 8 AUTO REFRESH commands.
 348         */
 349        for (idx = 0; idx < 8; idx++) {
 350                lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 351                asm("sync;msync");
 352                *sdram_addr = 0xff;
 353                ppcDcbf((unsigned long) sdram_addr);
 354                udelay(100);
 355        }
 356
 357        /*
 358         * Issue 8 MODE-set command.
 359         */
 360        lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 361        asm("sync;msync");
 362        *sdram_addr = 0xff;
 363        ppcDcbf((unsigned long) sdram_addr);
 364        udelay(100);
 365
 366        /*
 367         * Issue NORMAL OP command.
 368         */
 369        lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 370        asm("sync;msync");
 371        *sdram_addr = 0xff;
 372        ppcDcbf((unsigned long) sdram_addr);
 373        udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 374
 375#endif  /* enable SDRAM init */
 376}
 377
 378#if defined(CONFIG_PCI)
 379/* For some reason the Tundra PCI bridge shows up on itself as a
 380 * different device.  Work around that by refusing to configure it.
 381 */
 382void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
 383
 384static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 385        {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
 386        {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
 387        {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
 388                mpc85xx_config_via_usbide, {0,0,0}},
 389        {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
 390                mpc85xx_config_via_usb, {0,0,0}},
 391        {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
 392                mpc85xx_config_via_usb2, {0,0,0}},
 393        {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
 394                mpc85xx_config_via_power, {0,0,0}},
 395        {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
 396                mpc85xx_config_via_ac97, {0,0,0}},
 397        {},
 398};
 399
 400static struct pci_controller hose[] = {
 401        { config_table: pci_mpc85xxcds_config_table,},
 402#ifdef CONFIG_MPC85XX_PCI2
 403        {},
 404#endif
 405};
 406
 407#endif  /* CONFIG_PCI */
 408
 409void
 410pci_init_board(void)
 411{
 412#ifdef CONFIG_PCI
 413        pci_mpc85xx_init(hose);
 414#endif
 415}
 416
 417#if defined(CONFIG_OF_BOARD_SETUP)
 418void
 419ft_pci_setup(void *blob, bd_t *bd)
 420{
 421        int node, tmp[2];
 422        const char *path;
 423
 424        node = fdt_path_offset(blob, "/aliases");
 425        tmp[0] = 0;
 426        if (node >= 0) {
 427#ifdef CONFIG_PCI1
 428                path = fdt_getprop(blob, node, "pci0", NULL);
 429                if (path) {
 430                        tmp[1] = hose[0].last_busno - hose[0].first_busno;
 431                        do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 432                }
 433#endif
 434#ifdef CONFIG_MPC85XX_PCI2
 435                path = fdt_getprop(blob, node, "pci1", NULL);
 436                if (path) {
 437                        tmp[1] = hose[1].last_busno - hose[1].first_busno;
 438                        do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 439                }
 440#endif
 441        }
 442}
 443#endif
 444