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13#include <common.h>
14#include <command.h>
15#include <linux/ctype.h>
16#include <asm/io.h>
17#include <stdio_dev.h>
18#include <video_fb.h>
19#include "../common/ngpixis.h"
20#include <fsl_diu_fb.h>
21
22
23#define PX_CTL_ALTACC 0x80
24
25#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
26#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
27#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
28#define PX_BRDCFG0_ELBC_DIU 0x02
29
30#define PX_BRDCFG1_DVIEN 0x80
31#define PX_BRDCFG1_DFPEN 0x40
32#define PX_BRDCFG1_BACKLIGHT 0x20
33
34#define PMUXCR_ELBCDIU_MASK 0xc0000000
35#define PMUXCR_ELBCDIU_NOR16 0x80000000
36#define PMUXCR_ELBCDIU_DIU 0x40000000
37
38
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43
44
45
46#define AD_BYTE_F 0x10000000
47#define AD_ALPHA_C_SHIFT 25
48#define AD_BLUE_C_SHIFT 23
49#define AD_GREEN_C_SHIFT 21
50#define AD_RED_C_SHIFT 19
51#define AD_PIXEL_S_SHIFT 16
52#define AD_COMP_3_SHIFT 12
53#define AD_COMP_2_SHIFT 8
54#define AD_COMP_1_SHIFT 4
55#define AD_COMP_0_SHIFT 0
56
57
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60
61
62static u8 px_brdcfg0;
63static u32 pmuxcr;
64static void *lbc_lcs0_ba;
65static void *lbc_lcs1_ba;
66static u32 old_br0, old_or0, old_br1, old_or1;
67static u32 new_br0, new_or0, new_br1, new_or1;
68
69void diu_set_pixel_clock(unsigned int pixclock)
70{
71 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
72 unsigned long speed_ccb, temp;
73 u32 pixval;
74
75 speed_ccb = get_bus_freq(0);
76 temp = 1000000000 / pixclock;
77 temp *= 1000;
78 pixval = speed_ccb / temp;
79 debug("DIU pixval = %u\n", pixval);
80
81
82 temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
83 out_be32(&gur->clkdvdr, temp);
84 out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
85}
86
87int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
88{
89 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
90 const char *name;
91 u32 pixel_format;
92 u8 temp;
93 phys_addr_t phys0, phys1;
94
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106 new_br0 = old_br0 = get_lbc_br(0);
107 new_br1 = old_br1 = get_lbc_br(1);
108 new_or0 = old_or0 = get_lbc_or(0);
109 new_or1 = old_or1 = get_lbc_or(1);
110
111
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113
114
115
116 if ((old_br0 & BR_MSEL) != BR_MS_GPCM) {
117 new_br0 = (get_lbc_br(0) & BR_BA) | BR_V;
118 new_or0 = OR_AM_32KB | 0xFF7;
119 set_lbc_br(0, new_br0);
120 set_lbc_or(0, new_or0);
121 }
122 if ((old_br1 & BR_MSEL) != BR_MS_GPCM) {
123 new_br1 = (get_lbc_br(1) & BR_BA) | BR_V;
124 new_or1 = OR_AM_32KB | 0xFF7;
125 set_lbc_br(1, new_br1);
126 set_lbc_or(1, new_or1);
127 }
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138
139#ifdef CONFIG_PHYS_64BIT
140 phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA);
141 phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA);
142#else
143 phys0 = old_br0 & old_or0 & BR_BA;
144 phys1 = old_br1 & old_or1 & BR_BA;
145#endif
146
147
148 lbc_lcs0_ba = map_physmem(phys0, 1, 0);
149 lbc_lcs1_ba = map_physmem(phys1, 1, 0);
150
151 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
152 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
153 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
154 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
155 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
156
157 temp = in_8(&pixis->brdcfg1);
158
159 if (strncmp(port, "lvds", 4) == 0) {
160
161 temp &= ~PX_BRDCFG1_DVIEN;
162
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166 temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
167 name = "Single-Link LVDS";
168 } else {
169
170 temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
171 temp |= PX_BRDCFG1_DVIEN;
172 name = "DVI";
173 }
174
175 printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
176 out_8(&pixis->brdcfg1, temp);
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183 setbits_8(&pixis->csr, PX_CTL_ALTACC);
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189 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
190 px_brdcfg0 = in_8(lbc_lcs1_ba);
191 out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
192 in_8(lbc_lcs1_ba);
193
194
195 clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
196 pmuxcr = in_be32(&gur->pmuxcr);
197
198 return fsl_diu_init(xres, yres, pixel_format, 0);
199}
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215
216static int set_mux_to_lbc(void)
217{
218 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
219
220
221 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
222 PMUXCR_ELBCDIU_NOR16) {
223
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227
228 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
229 out_8(lbc_lcs1_ba, px_brdcfg0);
230 in_8(lbc_lcs1_ba);
231
232
233 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
234 clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
235
236
237 out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
238 PMUXCR_ELBCDIU_NOR16);
239 in_be32(&gur->pmuxcr);
240
241
242 set_lbc_br(0, old_br0);
243 set_lbc_or(0, old_or0);
244 set_lbc_br(1, old_br1);
245 set_lbc_or(1, old_or1);
246
247 return 1;
248 }
249
250 return 0;
251}
252
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256
257
258static void set_mux_to_diu(void)
259{
260 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
261
262
263 set_lbc_br(0, new_br0);
264 set_lbc_or(0, new_or0);
265 set_lbc_br(1, new_br1);
266 set_lbc_or(1, new_or1);
267
268
269 setbits_8(&pixis->csr, PX_CTL_ALTACC);
270
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272 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
273 out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
274 in_8(lbc_lcs1_ba);
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277 out_be32(&gur->pmuxcr, pmuxcr);
278 in_be32(&gur->pmuxcr);
279}
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286
287u8 pixis_read(unsigned int reg)
288{
289 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
290
291
292 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
293 PMUXCR_ELBCDIU_NOR16) {
294 out_8(lbc_lcs0_ba, reg);
295 return in_8(lbc_lcs1_ba);
296 } else {
297 void *p = (void *)PIXIS_BASE;
298
299 return in_8(p + reg);
300 }
301}
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308
309void pixis_write(unsigned int reg, u8 value)
310{
311 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
312
313
314 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
315 PMUXCR_ELBCDIU_NOR16) {
316 out_8(lbc_lcs0_ba, reg);
317 out_8(lbc_lcs1_ba, value);
318
319 in_8(lbc_lcs1_ba);
320 } else {
321 void *p = (void *)PIXIS_BASE;
322
323 out_8(p + reg, value);
324 }
325}
326
327void pixis_bank_reset(void)
328{
329
330
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333 set_mux_to_lbc();
334
335 out_8(&pixis->vctl, 0);
336 out_8(&pixis->vctl, 1);
337
338 while (1);
339}
340
341#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
342
343void flash_write8(u8 value, void *addr)
344{
345 int sw = set_mux_to_lbc();
346
347 __raw_writeb(value, addr);
348 if (sw) {
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356 __raw_readb(addr);
357 set_mux_to_diu();
358 }
359}
360
361void flash_write16(u16 value, void *addr)
362{
363 int sw = set_mux_to_lbc();
364
365 __raw_writew(value, addr);
366 if (sw) {
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374 __raw_readb(addr);
375 set_mux_to_diu();
376 }
377}
378
379void flash_write32(u32 value, void *addr)
380{
381 int sw = set_mux_to_lbc();
382
383 __raw_writel(value, addr);
384 if (sw) {
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389
390
391
392 __raw_readb(addr);
393 set_mux_to_diu();
394 }
395}
396
397void flash_write64(u64 value, void *addr)
398{
399 int sw = set_mux_to_lbc();
400 uint32_t *p = addr;
401
402
403
404
405
406 __asm__ __volatile__(
407 "stw%U0%X0 %2,%0;\n"
408 "stw%U1%X1 %3,%1;\n"
409 : "=m" (*p), "=m" (*(p + 1))
410 : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
411
412 if (sw) {
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419
420
421
422 __raw_readb(addr + 4);
423 set_mux_to_diu();
424 }
425}
426
427u8 flash_read8(void *addr)
428{
429 u8 ret;
430
431 int sw = set_mux_to_lbc();
432
433 ret = __raw_readb(addr);
434 if (sw)
435 set_mux_to_diu();
436
437 return ret;
438}
439
440u16 flash_read16(void *addr)
441{
442 u16 ret;
443
444 int sw = set_mux_to_lbc();
445
446 ret = __raw_readw(addr);
447 if (sw)
448 set_mux_to_diu();
449
450 return ret;
451}
452
453u32 flash_read32(void *addr)
454{
455 u32 ret;
456
457 int sw = set_mux_to_lbc();
458
459 ret = __raw_readl(addr);
460 if (sw)
461 set_mux_to_diu();
462
463 return ret;
464}
465
466u64 flash_read64(void *addr)
467{
468 u64 ret;
469
470 int sw = set_mux_to_lbc();
471
472
473 ret = *(volatile u64 *)addr;
474 if (sw)
475 set_mux_to_diu();
476
477 return ret;
478}
479
480#endif
481