LXR uboot/board/logicpd/omap3som/omap3logic.c

   1/*
   2 * (C) Copyright 2011
   3 * Logic Product Development <www.logicpd.com>
   4 *
   5 * Author :
   6 *      Peter Barada <peter.barada@logicpd.com>
   7 *
   8 * Derived from Beagle Board and 3430 SDP code by
   9 *      Richard Woodruff <r-woodruff2@ti.com>
  10 *      Syed Mohammed Khasim <khasim@ti.com>
  11 *
  12 * See file CREDITS for list of people who contributed to this
  13 * project.
  14 *
  15 * This program is free software; you can redistribute it and/or
  16 * modify it under the terms of the GNU General Public License as
  17 * published by the Free Software Foundation; either version 2 of
  18 * the License, or (at your option) any later version.
  19 *
  20 * This program is distributed in the hope that it will be useful,
  21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 * GNU General Public License for more details.
  24 *
  25 * You should have received a copy of the GNU General Public License
  26 * along with this program; if not, write to the Free Software
  27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28 * MA 02111-1307 USA
  29 */
  30#include <common.h>
  31#include <netdev.h>
  32#include <flash.h>
  33#include <nand.h>
  34#include <i2c.h>
  35#include <twl4030.h>
  36#include <asm/io.h>
  37#include <asm/arch/mmc_host_def.h>
  38#include <asm/arch/mux.h>
  39#include <asm/arch/mem.h>
  40#include <asm/arch/sys_proto.h>
  41#include <asm/gpio.h>
  42#include <asm/mach-types.h>
  43#include "omap3logic.h"
  44
  45DECLARE_GLOBAL_DATA_PTR;
  46
  47/*
  48 * two dimensional array of strucures containining board name and Linux
  49 * machine IDs; row it selected based on CPU column is slected based
  50 * on hsusb0_data5 pin having a pulldown resistor
  51 */
  52static struct board_id {
  53        char *name;
  54        int machine_id;
  55} boards[2][2] = {
  56        {
  57                {
  58                        .name           = "OMAP35xx SOM LV",
  59                        .machine_id     = MACH_TYPE_OMAP3530_LV_SOM,
  60                },
  61                {
  62                        .name           = "OMAP35xx Torpedo",
  63                        .machine_id     = MACH_TYPE_OMAP3_TORPEDO,
  64                },
  65        },
  66        {
  67                {
  68                        .name           = "DM37xx SOM LV",
  69                        .machine_id     = MACH_TYPE_DM3730_SOM_LV,
  70                },
  71                {
  72                        .name           = "DM37xx Torpedo",
  73                        .machine_id     = MACH_TYPE_DM3730_TORPEDO,
  74                },
  75        },
  76};
  77
  78/*
  79 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
  80 */
  81#define BOARD_ID_GPIO   189 /* hsusb0_data5 pin */
  82
  83/*
  84 * Routine: board_init
  85 * Description: Early hardware init.
  86 */
  87int board_init(void)
  88{
  89        struct board_id *board;
  90        unsigned int val;
  91
  92        gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  93
  94        /* boot param addr */
  95        gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  96
  97        /*
  98         * To identify between a SOM LV and Torpedo module,
  99         * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
 100         * Drive the pin (and let it soak), then read it back.
 101         * If the pin is still high its a Torpedo.  If low its a SOM LV
 102         */
 103
 104        /* Mux hsusb0_data5 as a GPIO */
 105        MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M4));
 106
 107        if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
 108
 109                /*
 110                 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
 111                 * will drain the voltage.
 112                 */
 113                gpio_direction_output(BOARD_ID_GPIO, 0);
 114                gpio_set_value(BOARD_ID_GPIO, 1);
 115
 116                /* Let it soak for a bit */
 117                sdelay(0x100);
 118
 119                /*
 120                 * Read state of BOARD_ID_GPIO as an input and if its set.
 121                 * If so the board is a Torpedo
 122                 */
 123                gpio_direction_input(BOARD_ID_GPIO);
 124                val = gpio_get_value(BOARD_ID_GPIO);
 125                gpio_free(BOARD_ID_GPIO);
 126
 127                board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
 128                printf("Board: %s\n", board->name);
 129
 130                /* Set the machine_id passed to Linux */
 131                gd->bd->bi_arch_number = board->machine_id;
 132        }
 133
 134        /* restore hsusb0_data5 pin as hsusb0_data5 */
 135        MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0));
 136
 137        return 0;
 138}
 139
 140#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 141int board_mmc_init(bd_t *bis)
 142{
 143        return omap_mmc_init(0, 0, 0, -1, -1);
 144}
 145#endif
 146
 147#ifdef CONFIG_SMC911X
 148/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
 149static const u32 gpmc_lan92xx_config[] = {
 150        NET_LAN92XX_GPMC_CONFIG1,
 151        NET_LAN92XX_GPMC_CONFIG2,
 152        NET_LAN92XX_GPMC_CONFIG3,
 153        NET_LAN92XX_GPMC_CONFIG4,
 154        NET_LAN92XX_GPMC_CONFIG5,
 155        NET_LAN92XX_GPMC_CONFIG6,
 156};
 157
 158int board_eth_init(bd_t *bis)
 159{
 160        enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
 161                        CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
 162
 163        return smc911x_initialize(0, CONFIG_SMC911X_BASE);
 164}
 165#endif
 166
 167/*
 168 * IEN  - Input Enable
 169 * IDIS - Input Disable
 170 * PTD  - Pull type Down
 171 * PTU  - Pull type Up
 172 * DIS  - Pull type selection is inactive
 173 * EN   - Pull type selection is active
 174 * M0   - Mode 0
 175 * The commented string gives the final mux configuration for that pin
 176 */
 177
 178/*
 179 * Routine: set_muxconf_regs
 180 * Description: Setting up the configuration Mux registers specific to the
 181 *              hardware. Many pins need to be moved from protect to primary
 182 *              mode.
 183 */
 184void set_muxconf_regs(void)
 185{
 186        /*GPMC*/
 187        MUX_VAL(CP(GPMC_A1),            (IDIS | PTU | EN  | M0));
 188        MUX_VAL(CP(GPMC_A2),            (IDIS | PTU | EN  | M0));
 189        MUX_VAL(CP(GPMC_A3),            (IDIS | PTU | EN  | M0));
 190        MUX_VAL(CP(GPMC_A4),            (IDIS | PTU | EN  | M0));
 191        MUX_VAL(CP(GPMC_A5),            (IDIS | PTU | EN  | M0));
 192        MUX_VAL(CP(GPMC_A6),            (IDIS | PTU | EN  | M0));
 193        MUX_VAL(CP(GPMC_A7),            (IDIS | PTU | EN  | M0));
 194        MUX_VAL(CP(GPMC_A8),            (IDIS | PTU | EN  | M0));
 195        MUX_VAL(CP(GPMC_A9),            (IDIS | PTU | EN  | M0));
 196        MUX_VAL(CP(GPMC_A10),           (IDIS | PTU | EN  | M0));
 197        MUX_VAL(CP(GPMC_D0),            (IEN  | PTU | EN  | M0));
 198        MUX_VAL(CP(GPMC_D1),            (IEN  | PTU | EN  | M0));
 199        MUX_VAL(CP(GPMC_D2),            (IEN  | PTU | EN  | M0));
 200        MUX_VAL(CP(GPMC_D3),            (IEN  | PTU | EN  | M0));
 201        MUX_VAL(CP(GPMC_D4),            (IEN  | PTU | EN  | M0));
 202        MUX_VAL(CP(GPMC_D5),            (IEN  | PTU | EN  | M0));
 203        MUX_VAL(CP(GPMC_D6),            (IEN  | PTU | EN  | M0));
 204        MUX_VAL(CP(GPMC_D7),            (IEN  | PTU | EN  | M0));
 205        MUX_VAL(CP(GPMC_D8),            (IEN  | PTU | EN  | M0));
 206        MUX_VAL(CP(GPMC_D9),            (IEN  | PTU | EN  | M0));
 207        MUX_VAL(CP(GPMC_D10),           (IEN  | PTU | EN  | M0));
 208        MUX_VAL(CP(GPMC_D11),           (IEN  | PTU | EN  | M0));
 209        MUX_VAL(CP(GPMC_D12),           (IEN  | PTU | EN  | M0));
 210        MUX_VAL(CP(GPMC_D13),           (IEN  | PTU | EN  | M0));
 211        MUX_VAL(CP(GPMC_D14),           (IEN  | PTU | EN  | M0));
 212        MUX_VAL(CP(GPMC_D15),           (IEN  | PTU | EN  | M0));
 213        MUX_VAL(CP(GPMC_NCS0),          (IDIS | PTU | EN  | M0));
 214        MUX_VAL(CP(GPMC_NCS1),          (IDIS | PTU | EN  | M0));
 215        MUX_VAL(CP(GPMC_NCS2),          (IDIS | PTU | EN  | M0));
 216        MUX_VAL(CP(GPMC_NCS3),          (IDIS | PTD | DIS | M0));
 217        MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | DIS | M4));
 218        MUX_VAL(CP(GPMC_NCS7),          (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
 219        MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTU | EN  | M0));
 220        MUX_VAL(CP(GPMC_WAIT1),         (IEN  | PTU | EN  | M0));
 221
 222        /*Expansion card  */
 223        MUX_VAL(CP(MMC1_CLK),           (IDIS | PTU | EN  | M0));
 224        MUX_VAL(CP(MMC1_CMD),           (IEN  | PTU | EN  | M0));
 225        MUX_VAL(CP(MMC1_DAT0),          (IEN  | PTU | EN  | M0));
 226        MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | EN  | M0));
 227        MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | EN  | M0));
 228        MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | EN  | M0));
 229
 230        /* Serial Console */
 231        MUX_VAL(CP(UART1_TX),           (IDIS | PTD | DIS | M0));
 232        MUX_VAL(CP(UART1_RTS),          (IDIS | PTD | DIS | M0));
 233        MUX_VAL(CP(UART1_CTS),          (IEN  | PTU | DIS | M0));
 234        MUX_VAL(CP(UART1_RX),           (IEN  | PTD | DIS | M0));
 235
 236        /* I2C */
 237        MUX_VAL(CP(I2C2_SCL),           (IEN  | PTU | EN  | M0));
 238        MUX_VAL(CP(I2C2_SDA),           (IEN  | PTU | EN  | M0));
 239        MUX_VAL(CP(I2C3_SCL),           (IEN  | PTU | EN  | M0));
 240        MUX_VAL(CP(I2C3_SDA),           (IEN  | PTU | EN  | M0));
 241
 242        MUX_VAL(CP(HDQ_SIO),            (IEN  | PTU | EN  | M0));
 243
 244        /*Control and debug */
 245        MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0));
 246        MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0));
 247        MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTD | DIS | M0));
 248        MUX_VAL(CP(SYS_CLKOUT2),        (IEN  | PTU | EN  | M0));
 249        MUX_VAL(CP(JTAG_nTRST),         (IEN  | PTD | DIS | M0));
 250        MUX_VAL(CP(SDRC_CKE0),          (IDIS | PTU | EN  | M0));
 251}
 252