1/* 2 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering 3 * 4 * Copyright (C) 2006 Micronas GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22#ifndef _SCC_H 23#define _SCC_H 24 25#define DMA_READ 0 /* SCC read DMA */ 26#define DMA_WRITE 1 /* SCC write DMA */ 27 28#define DMA_LINEAR 0 /* DMA linear buffer access method */ 29#define DMA_CYCLIC 1 /* DMA cyclic buffer access method */ 30 31#define DMA_START 0 /* DMA command - start DMA */ 32#define DMA_STOP 1 /* DMA command - stop DMA */ 33#define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */ 34#define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */ 35 36#define AGU_ACTIVE 0 /* enable AGU address calculation */ 37#define AGU_BYPASS 1 /* set AGU to bypass mode */ 38 39#define USE_NO_FH 0 /* order the DMA to not use FH */ 40#define USE_FH 1 /* order the DMA to work with FH*/ 41 42#define SCC_DBG_IDLE 0 /* DEBUG status (idle interfaces) */ 43#define SCC_DBG_SYNC_RES 0x0001 /* synchronuous reset */ 44 45#define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/ 46#define TO_DMA_CFG 2 /* takeover command for the DMA config*/ 47 48#define DMA_CMD_RESET 0 49#define DMA_CMD_SETUP 1 50#define DMA_CMD_START 2 51#define DMA_CMD_STOP 3 52 53#define DMA_STATE_RESET 0 54#define DMA_STATE_SETUP 1 55#define DMA_STATE_START 2 56#define DMA_STATE_ERROR 3 57 58#define SRMD 0 59#define STRM_D 1 60#define STRM_P 2 61 62/* 63 * Slowest Monterey domain is DVP 27 MHz (324/27 = 12; 12*16 = 192 CPU clocks) 64 */ 65#define RESET_TIME 2 /* cycle calc see in SCC_Reset */ 66 67struct scc_descriptor { 68 char *pu_name; /* PU identifier */ 69 char *scc_instance; /* SCC Name */ 70 u32 profile; /* SCC VCI_D profile */ 71 72 u32 base_address; /* base address of the SCC unit reg shell*/ 73 74 /* SCS Interconnect configuration */ 75 u32 p_scc_id; /* instance number of SCC unit */ 76 u32 p_mci_id; /* memory channel ID */ 77 78 /* DMA Registers configuration */ 79 u32 p_dma_channels_rd; /* Number of Read DMA channels */ 80 u32 p_dma_channels_wr; /* Number of Write DMA channels */ 81 82 u32 p_dma_packet_desc; /* Number of packet descriptors */ 83 u32 p_dma_mci_desc; /* Number of MCI_CFG Descriptors */ 84 85 int use_fh; /* the flag tells if SCC uses an FH */ 86 87 int p_si2ocp_id; /* instance number of SI2OCP unit */ 88 int hw_dma_cfg; /* HW or SW DMA config flag */ 89 int hw_dma_start; /* HW or SW DMA start/stop flag */ 90 91 u32 *buffer_tag_list; /* list of the buffer tags available */ 92 u32 *csize_list; /* list of the valid CSIZE values */ 93}; 94 95struct scc_dma_state { 96 u32 scc_id:8; /* SCC id */ 97 u32 dma_id:8; /* DMA id, used for match with array idx*/ 98 u32 buffer_tag:8; /* mem buf tag, assigned to this DMA */ 99 u32 dma_status:2; /* state of DMA, of the DMA_STATE_ const*/ 100 u32 dma_drs:2; /* DMA dir, either DMA_READ or DMA_WRITE*/ 101 u32 dma_cmd:4; /* last executed command on this DMA */ 102}; 103 104union scc_cmd { 105 u32 reg; 106 struct { 107 u32 res1:19; /* reserved */ 108 u32 drs:1; /* DMA Register Set */ 109 u32 rid:2; /* Register Identifier */ 110 u32 id:6; /* DMA Identifier */ 111 u32 action:4; /* DMA Command encoding */ 112 } bits; 113}; 114 115union scc_dma_cfg { 116 u32 reg; 117 struct { 118 u32 res1:17; /* reserved */ 119 u32 agu_mode:1; /* AGU Mode */ 120 u32 res2:1; /* reserved */ 121 u32 fh_mode:1; /* Fifo Handler */ 122 u32 buffer_type:1; /* Defines type of mem buffers */ 123 u32 mci_cfg_id:1; /* MCI_CFG register selector */ 124 u32 packet_cfg_id:1; /* PACKET_CFG register selector */ 125 u32 buffer_id:8; /* DMA Buffer Identifier */ 126 } bits; 127}; 128 129union scc_debug { 130 u32 reg; 131 struct { 132 u32 res1:20; /* reserved */ 133 u32 arg:8; /* SCC Debug Command Argument (#) */ 134 u32 cmd:4; /* SCC Debug Command Register */ 135 } bits; 136}; 137 138union scc_softwareconfiguration { 139 u32 reg; 140 struct { 141 u32 res1:28; /* reserved */ 142 u32 clock_status:1; /* clock on/off */ 143 u32 packet_select:1; /* active SCC packet id */ 144 u32 enable_status:1; /* enabled [1/0] */ 145 u32 active_status:1; /* 1=active 0=reset */ 146 } bits; 147}; 148 149/* 150 * System on Chip Channel ID 151 */ 152enum scc_id { 153 SCC_NULL = -1, /* illegal SCC identifier */ 154 SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */ 155 SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */ 156 SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */ 157 SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */ 158 SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */ 159 SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */ 160 SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */ 161 SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */ 162 SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */ 163 SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */ 164 SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */ 165 SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */ 166 SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */ 167 SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */ 168 SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */ 169 SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */ 170 SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */ 171 SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */ 172 SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */ 173 SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */ 174 SCC_TSIO_WR, /* SCC_TSIO Write channel */ 175 SCC_TSIO_RD, /* SCC_TSIO Read channel */ 176 SCC_TSD_WR, /* SCC_TSD Write channel */ 177 SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */ 178 SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */ 179 SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */ 180 SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */ 181 SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */ 182 SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */ 183 SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */ 184 SCC_GA_WR, /* SCC_GA Write channel */ 185 SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */ 186 SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */ 187 SCC_AD_RD, /* SCC_AD Read channel */ 188 SCC_AD_WR, /* SCC_AD Write channel */ 189 SCC_ABP_RD, /* SCC_ABP Read channel */ 190 SCC_ABP_WR, /* SCC_ABP Write channel */ 191 SCC_EBI_RW, /* SCC_EBI Read/Write channel */ 192 SCC_USB_RW, /* SCC_USB Read/Write channel */ 193 SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */ 194 SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */ 195 SCC_MAX /* maximum limit on the SCC id */ 196}; 197 198int scc_set_usb_address_generation_mode(u32 agu_mode); 199int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs); 200int scc_setup_dma(enum scc_id id, u32 buffer_tag, 201 u32 type, u32 fh_mode, u32 drs, u32 dma_id); 202int scc_enable(enum scc_id id, u32 value); 203int scc_reset(enum scc_id id, u32 value); 204 205#endif /* _SCC_H */ 206