uboot/board/samsung/origen/lowlevel_init.S
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   1/*
   2 * Lowlevel setup for ORIGEN board based on EXYNOS4210
   3 *
   4 * Copyright (C) 2011 Samsung Electronics
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#include <config.h>
  26#include <version.h>
  27#include <asm/arch/cpu.h>
  28#include "origen_setup.h"
  29/*
  30 * Register usages:
  31 *
  32 * r5 has zero always
  33 * r7 has GPIO part1 base 0x11400000
  34 * r6 has GPIO part2 base 0x11000000
  35 */
  36
  37_TEXT_BASE:
  38        .word   CONFIG_SYS_TEXT_BASE
  39
  40        .globl lowlevel_init
  41lowlevel_init:
  42        push    {lr}
  43
  44        /* r5 has always zero */
  45        mov     r5, #0
  46        ldr     r7, =EXYNOS4_GPIO_PART1_BASE
  47        ldr     r6, =EXYNOS4_GPIO_PART2_BASE
  48
  49        /* check reset status */
  50        ldr     r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
  51        ldr     r1, [r0]
  52
  53        /* AFTR wakeup reset */
  54        ldr     r2, =S5P_CHECK_DIDLE
  55        cmp     r1, r2
  56        beq     exit_wakeup
  57
  58        /* LPA wakeup reset */
  59        ldr     r2, =S5P_CHECK_LPA
  60        cmp     r1, r2
  61        beq     exit_wakeup
  62
  63        /* Sleep wakeup reset */
  64        ldr     r2, =S5P_CHECK_SLEEP
  65        cmp     r1, r2
  66        beq     wakeup_reset
  67
  68        /*
  69         * If U-boot is already running in ram, no need to relocate U-Boot.
  70         * Memory controller must be configured before relocating U-Boot
  71         * in ram.
  72         */
  73        ldr     r0, =0x0ffffff          /* r0 <- Mask Bits*/
  74        bic     r1, pc, r0              /* pc <- current addr of code */
  75                                        /* r1 <- unmasked bits of pc */
  76        ldr     r2, _TEXT_BASE          /* r2 <- original base addr in ram */
  77        bic     r2, r2, r0              /* r2 <- unmasked bits of r2*/
  78        cmp     r1, r2                  /* compare r1, r2 */
  79        beq     1f                      /* r0 == r1 then skip sdram init */
  80
  81        /* init system clock */
  82        bl system_clock_init
  83
  84        /* Memory initialize */
  85        bl mem_ctrl_asm_init
  86
  871:
  88        /* for UART */
  89        bl uart_asm_init
  90        bl tzpc_init
  91        pop     {pc}
  92
  93wakeup_reset:
  94        bl system_clock_init
  95        bl mem_ctrl_asm_init
  96        bl tzpc_init
  97
  98exit_wakeup:
  99        /* Load return address and jump to kernel */
 100        ldr     r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
 101
 102        /* r1 = physical address of exynos4210_cpu_resume function */
 103        ldr     r1, [r0]
 104
 105        /* Jump to kernel*/
 106        mov     pc, r1
 107        nop
 108        nop
 109
 110/*
 111 * system_clock_init: Initialize core clock and bus clock.
 112 * void system_clock_init(void)
 113 */
 114system_clock_init:
 115        push    {lr}
 116        ldr     r0, =EXYNOS4_CLOCK_BASE
 117
 118        /* APLL(1), MPLL(1), CORE(0), HPM(0) */
 119        ldr     r1, =CLK_SRC_CPU_VAL
 120        ldr     r2, =CLK_SRC_CPU_OFFSET
 121        str     r1, [r0, r2]
 122
 123        /* wait ?us */
 124        mov     r1, #0x10000
 1252:      subs    r1, r1, #1
 126        bne     2b
 127
 128        ldr     r1, =CLK_SRC_TOP0_VAL
 129        ldr     r2, =CLK_SRC_TOP0_OFFSET
 130        str     r1, [r0, r2]
 131
 132        ldr     r1, =CLK_SRC_TOP1_VAL
 133        ldr     r2, =CLK_SRC_TOP1_OFFSET
 134        str     r1, [r0, r2]
 135
 136        /* DMC */
 137        ldr     r1, =CLK_SRC_DMC_VAL
 138        ldr     r2, =CLK_SRC_DMC_OFFSET
 139        str     r1, [r0, r2]
 140
 141        /*CLK_SRC_LEFTBUS */
 142        ldr     r1, =CLK_SRC_LEFTBUS_VAL
 143        ldr     r2, =CLK_SRC_LEFTBUS_OFFSET
 144        str     r1, [r0, r2]
 145
 146        /*CLK_SRC_RIGHTBUS */
 147        ldr     r1, =CLK_SRC_RIGHTBUS_VAL
 148        ldr     r2, =CLK_SRC_RIGHTBUS_OFFSET
 149        str     r1, [r0, r2]
 150
 151        /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
 152        ldr     r1, =CLK_SRC_FSYS_VAL
 153        ldr     r2, =CLK_SRC_FSYS_OFFSET
 154        str     r1, [r0, r2]
 155
 156        /* UART[0:4] */
 157        ldr     r1, =CLK_SRC_PERIL0_VAL
 158        ldr     r2, =CLK_SRC_PERIL0_OFFSET
 159        str     r1, [r0, r2]
 160
 161        /* CAM , FIMC 0-3 */
 162        ldr     r1, =CLK_SRC_CAM_VAL
 163        ldr     r2, =CLK_SRC_CAM_OFFSET
 164        str     r1, [r0, r2]
 165
 166        /* MFC */
 167        ldr     r1, =CLK_SRC_MFC_VAL
 168        ldr     r2, =CLK_SRC_MFC_OFFSET
 169        str     r1, [r0, r2]
 170
 171        /* G3D */
 172        ldr     r1, =CLK_SRC_G3D_VAL
 173        ldr     r2, =CLK_SRC_G3D_OFFSET
 174        str     r1, [r0, r2]
 175
 176        /* LCD0 */
 177        ldr     r1, =CLK_SRC_LCD0_VAL
 178        ldr     r2, =CLK_SRC_LCD0_OFFSET
 179        str     r1, [r0, r2]
 180
 181        /* wait ?us */
 182        mov     r1, #0x10000
 1833:      subs    r1, r1, #1
 184        bne     3b
 185
 186        /* CLK_DIV_CPU0 */
 187        ldr     r1, =CLK_DIV_CPU0_VAL
 188        ldr     r2, =CLK_DIV_CPU0_OFFSET
 189        str     r1, [r0, r2]
 190
 191        /* CLK_DIV_CPU1 */
 192        ldr     r1, =CLK_DIV_CPU1_VAL
 193        ldr     r2, =CLK_DIV_CPU1_OFFSET
 194        str     r1, [r0, r2]
 195
 196        /* CLK_DIV_DMC0 */
 197        ldr     r1, =CLK_DIV_DMC0_VAL
 198        ldr     r2, =CLK_DIV_DMC0_OFFSET
 199        str     r1, [r0, r2]
 200
 201        /*CLK_DIV_DMC1 */
 202        ldr     r1, =CLK_DIV_DMC1_VAL
 203        ldr     r2, =CLK_DIV_DMC1_OFFSET
 204        str     r1, [r0, r2]
 205
 206        /* CLK_DIV_LEFTBUS */
 207        ldr     r1, =CLK_DIV_LEFTBUS_VAL
 208        ldr     r2, =CLK_DIV_LEFTBUS_OFFSET
 209        str     r1, [r0, r2]
 210
 211        /* CLK_DIV_RIGHTBUS */
 212        ldr     r1, =CLK_DIV_RIGHTBUS_VAL
 213        ldr     r2, =CLK_DIV_RIGHTBUS_OFFSET
 214        str     r1, [r0, r2]
 215
 216        /* CLK_DIV_TOP */
 217        ldr     r1, =CLK_DIV_TOP_VAL
 218        ldr     r2, =CLK_DIV_TOP_OFFSET
 219        str     r1, [r0, r2]
 220
 221        /* MMC[0:1] */
 222        ldr     r1, =CLK_DIV_FSYS1_VAL          /* 800(MPLL) / (15 + 1) */
 223        ldr     r2, =CLK_DIV_FSYS1_OFFSET
 224        str     r1, [r0, r2]
 225
 226        /* MMC[2:3] */
 227        ldr     r1, =CLK_DIV_FSYS2_VAL          /* 800(MPLL) / (15 + 1) */
 228        ldr     r2, =CLK_DIV_FSYS2_OFFSET
 229        str     r1, [r0, r2]
 230
 231        /* MMC4 */
 232        ldr     r1, =CLK_DIV_FSYS3_VAL          /* 800(MPLL) / (15 + 1) */
 233        ldr     r2, =CLK_DIV_FSYS3_OFFSET
 234        str     r1, [r0, r2]
 235
 236        /* CLK_DIV_PERIL0: UART Clock Divisors */
 237        ldr     r1, =CLK_DIV_PERIL0_VAL
 238        ldr     r2, =CLK_DIV_PERIL0_OFFSET
 239        str     r1, [r0, r2]
 240
 241        /* CAM, FIMC 0-3: CAM Clock Divisors */
 242        ldr     r1, =CLK_DIV_CAM_VAL
 243        ldr     r2, =CLK_DIV_CAM_OFFSET
 244        str     r1, [r0, r2]
 245
 246        /* CLK_DIV_MFC: MFC Clock Divisors */
 247        ldr     r1, =CLK_DIV_MFC_VAL
 248        ldr     r2, =CLK_DIV_MFC_OFFSET
 249        str     r1, [r0, r2]
 250
 251        /* CLK_DIV_G3D: G3D Clock Divisors */
 252        ldr     r1, =CLK_DIV_G3D_VAL
 253        ldr     r2, =CLK_DIV_G3D_OFFSET
 254        str     r1, [r0, r2]
 255
 256        /* CLK_DIV_LCD0: LCD0 Clock Divisors */
 257        ldr     r1, =CLK_DIV_LCD0_VAL
 258        ldr     r2, =CLK_DIV_LCD0_OFFSET
 259        str     r1, [r0, r2]
 260
 261        /* Set PLL locktime */
 262        ldr     r1, =PLL_LOCKTIME
 263        ldr     r2, =APLL_LOCK_OFFSET
 264        str     r1, [r0, r2]
 265
 266        ldr     r1, =PLL_LOCKTIME
 267        ldr     r2, =MPLL_LOCK_OFFSET
 268        str     r1, [r0, r2]
 269
 270        ldr     r1, =PLL_LOCKTIME
 271        ldr     r2, =EPLL_LOCK_OFFSET
 272        str     r1, [r0, r2]
 273
 274        ldr     r1, =PLL_LOCKTIME
 275        ldr     r2, =VPLL_LOCK_OFFSET
 276        str     r1, [r0, r2]
 277
 278        /* APLL_CON1 */
 279        ldr     r1, =APLL_CON1_VAL
 280        ldr     r2, =APLL_CON1_OFFSET
 281        str     r1, [r0, r2]
 282
 283        /* APLL_CON0 */
 284        ldr     r1, =APLL_CON0_VAL
 285        ldr     r2, =APLL_CON0_OFFSET
 286        str     r1, [r0, r2]
 287
 288        /* MPLL_CON1 */
 289        ldr     r1, =MPLL_CON1_VAL
 290        ldr     r2, =MPLL_CON1_OFFSET
 291        str     r1, [r0, r2]
 292
 293        /* MPLL_CON0 */
 294        ldr     r1, =MPLL_CON0_VAL
 295        ldr     r2, =MPLL_CON0_OFFSET
 296        str     r1, [r0, r2]
 297
 298        /* EPLL */
 299        ldr     r1, =EPLL_CON1_VAL
 300        ldr     r2, =EPLL_CON1_OFFSET
 301        str     r1, [r0, r2]
 302
 303        /* EPLL_CON0 */
 304        ldr     r1, =EPLL_CON0_VAL
 305        ldr     r2, =EPLL_CON0_OFFSET
 306        str     r1, [r0, r2]
 307
 308        /* VPLL_CON1 */
 309        ldr     r1, =VPLL_CON1_VAL
 310        ldr     r2, =VPLL_CON1_OFFSET
 311        str     r1, [r0, r2]
 312
 313        /* VPLL_CON0 */
 314        ldr     r1, =VPLL_CON0_VAL
 315        ldr     r2, =VPLL_CON0_OFFSET
 316        str     r1, [r0, r2]
 317
 318        /* wait ?us */
 319        mov     r1, #0x30000
 3204:      subs    r1, r1, #1
 321        bne     4b
 322
 323        pop     {pc}
 324/*
 325 * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
 326 * void uart_asm_init(void)
 327 */
 328        .globl uart_asm_init
 329uart_asm_init:
 330
 331        /* setup UART0-UART3 GPIOs (part1) */
 332        mov     r0, r7
 333        ldr     r1, =EXYNOS4_GPIO_A0_CON_VAL
 334        str     r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
 335        ldr     r1, =EXYNOS4_GPIO_A1_CON_VAL
 336        str     r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
 337
 338        ldr r0, =EXYNOS4_UART_BASE
 339        add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
 340
 341        ldr     r1, =ULCON_VAL
 342        str     r1, [r0, #ULCON_OFFSET]
 343        ldr     r1, =UCON_VAL
 344        str     r1, [r0, #UCON_OFFSET]
 345        ldr     r1, =UFCON_VAL
 346        str     r1, [r0, #UFCON_OFFSET]
 347        ldr     r1, =UBRDIV_VAL
 348        str     r1, [r0, #UBRDIV_OFFSET]
 349        ldr     r1, =UFRACVAL_VAL
 350        str     r1, [r0, #UFRACVAL_OFFSET]
 351        mov     pc, lr
 352        nop
 353        nop
 354        nop
 355
 356/* Setting TZPC[TrustZone Protection Controller] */
 357tzpc_init:
 358        ldr     r0, =TZPC0_BASE
 359        mov     r1, #R0SIZE
 360        str     r1, [r0]
 361        mov     r1, #DECPROTXSET
 362        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
 363        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
 364        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
 365        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
 366
 367        ldr     r0, =TZPC1_BASE
 368        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
 369        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
 370        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
 371        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
 372
 373        ldr     r0, =TZPC2_BASE
 374        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
 375        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
 376        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
 377        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
 378
 379        ldr     r0, =TZPC3_BASE
 380        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
 381        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
 382        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
 383        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
 384
 385        ldr     r0, =TZPC4_BASE
 386        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
 387        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
 388        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
 389        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
 390
 391        ldr     r0, =TZPC5_BASE
 392        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
 393        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
 394        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
 395        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
 396
 397        mov     pc, lr
 398
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.