LXR uboot/board/ti/omap5912osk/lowlevel

   1/*
   2 * Board specific setup info
   3 *
   4 * (C) Copyright 2003
   5 * Texas Instruments, <www.ti.com>
   6 * Kshitij Gupta <Kshitij@ti.com>
   7 *
   8 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
   9 *
  10 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
  11 * See file CREDITS for list of people who contributed to this
  12 * project.
  13 *
  14 * This program is free software; you can redistribute it and/or
  15 * modify it under the terms of the GNU General Public License as
  16 * published by the Free Software Foundation; either version 2 of
  17 * the License, or (at your option) any later version.
  18 *
  19 * This program is distributed in the hope that it will be useful,
  20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22 * GNU General Public License for more details.
  23 *
  24 * You should have received a copy of the GNU General Public License
  25 * along with this program; if not, write to the Free Software
  26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27 * MA 02111-1307 USA
  28 */
  29
  30#include <config.h>
  31#include <version.h>
  32
  33#if defined(CONFIG_OMAP1610)
  34#include <./configs/omap1510.h>
  35#endif
  36
  37
  38_TEXT_BASE:
  39        .word   CONFIG_SYS_TEXT_BASE    /* sdram load addr from config.mk */
  40
  41.globl lowlevel_init
  42lowlevel_init:
  43
  44        /*------------------------------------------------------*
  45         * Ensure i-cache is enabled                            *
  46         * To configure TC regs without fetching instruction    *
  47         *------------------------------------------------------*/
  48        mrc     p15, 0, r0, c1, c0
  49        orr     r0, r0, #0x1000
  50        mcr     p15, 0, r0, c1, c0
  51
  52        /*------------------------------------------------------*
  53         *mask all IRQs by setting all bits in the INTMR default*
  54         *------------------------------------------------------*/
  55        mov     r1, #0xffffffff
  56        ldr     r0, =REG_IHL1_MIR
  57        str     r1, [r0]
  58        ldr     r0, =REG_IHL2_MIR
  59        str     r1, [r0]
  60
  61        /*------------------------------------------------------*
  62         * Set up ARM CLM registers (IDLECT1)                   *
  63         *------------------------------------------------------*/
  64        ldr     r0,     REG_ARM_IDLECT1
  65        ldr     r1,     VAL_ARM_IDLECT1
  66        str     r1,     [r0]
  67
  68        /*------------------------------------------------------*
  69         * Set up ARM CLM registers (IDLECT2)                   *
  70         *------------------------------------------------------*/
  71        ldr     r0,     REG_ARM_IDLECT2
  72        ldr     r1,     VAL_ARM_IDLECT2
  73        str     r1,     [r0]
  74
  75        /*------------------------------------------------------*
  76         * Set up ARM CLM registers (IDLECT3)                   *
  77         *------------------------------------------------------*/
  78        ldr     r0,     REG_ARM_IDLECT3
  79        ldr     r1,     VAL_ARM_IDLECT3
  80        str     r1,     [r0]
  81
  82        mov     r1,     #0x01               /* PER_EN bit */
  83        ldr     r0,     REG_ARM_RSTCT2
  84        strh    r1,     [r0]            /* CLKM; Peripheral reset. */
  85
  86        /* Set CLKM to Sync-Scalable */
  87        mov     r1,     #0x1000
  88        ldr     r0,     REG_ARM_SYSST
  89
  90        mov     r2,     #0
  911:      cmp     r2,     #1
  92        streqh  r1,     [r0]
  93        add     r2,     r2,     #1
  94        cmp     r2,     #0x100              /* wait for any bubbles to finish */
  95        bne     1b
  96
  97        ldr     r1,     VAL_ARM_CKCTL
  98        ldr     r0,     REG_ARM_CKCTL
  99        strh    r1,     [r0]
 100
 101        /* a few nops to let settle */
 102        nop
 103        nop
 104        nop
 105        nop
 106        nop
 107        nop
 108        nop
 109        nop
 110        nop
 111        nop
 112
 113        /* setup DPLL 1 */
 114        /* Ramp up the clock to 96Mhz */
 115        ldr     r1,     VAL_DPLL1_CTL
 116        ldr     r0,     REG_DPLL1_CTL
 117        strh    r1,     [r0]
 118        ands    r1,     r1,     #0x10       /* Check if PLL is enabled. */
 119        beq     lock_end                /* Do not look for lock if BYPASS selected */
 1202:
 121        ldrh    r1,     [r0]
 122        ands    r1,     r1,     #0x01       /* Check the LOCK bit.*/
 123        beq 2b                      /* loop until bit goes hi. */
 124lock_end:
 125
 126        /*------------------------------------------------------*
 127         * Turn off the watchdog during init...                 *
 128         *------------------------------------------------------*/
 129        ldr     r0,     REG_WATCHDOG
 130        ldr     r1,     WATCHDOG_VAL1
 131        str     r1,     [r0]
 132        ldr     r1,     WATCHDOG_VAL2
 133        str     r1,     [r0]
 134        ldr     r0,     REG_WSPRDOG
 135        ldr     r1,     WSPRDOG_VAL1
 136        str     r1,     [r0]
 137        ldr     r0,     REG_WWPSDOG
 138
 139watch1Wait:
 140        ldr     r1,     [r0]
 141        tst     r1,     #0x10
 142        bne     watch1Wait
 143
 144        ldr     r0,     REG_WSPRDOG
 145        ldr     r1,     WSPRDOG_VAL2
 146        str     r1,     [r0]
 147        ldr     r0,     REG_WWPSDOG
 148watch2Wait:
 149        ldr     r1,     [r0]
 150        tst     r1,     #0x10
 151        bne     watch2Wait
 152
 153        /* Set memory timings corresponding to the new clock speed */
 154        ldr     r3, VAL_SDRAM_CONFIG_SDF0
 155
 156        /* Check execution location to determine current execution location
 157         * and branch to appropriate initialization code.
 158         */
 159        mov     r0,     #0x10000000         /* Load physical SDRAM base. */
 160        mov     r1,     pc                  /* Get current execution location. */
 161        cmp     r1,     r0                  /* Compare. */
 162        bge     skip_sdram              /* Skip over EMIF-fast initialization if running from SDRAM. */
 163
 164        /* identify the device revision, -- TMX or TMP(TMS) */
 165        ldr     r0, REG_DEVICE_ID
 166        ldr     r1, [r0]
 167
 168        ldr     r0, VAL_DEVICE_ID_TMP
 169        mov     r1, r1, lsl #15
 170        mov     r1, r1, lsr #16
 171        cmp     r0, r1
 172        bne     skip_TMP_Patch
 173
 174        /* Enable TMP/TMS device new features */
 175        mov     r0, #1
 176        ldr     r1, REG_TC_EMIFF_DOUBLER
 177        str     r0, [r1]
 178
 179        /* Enable new ac parameters */
 180        mov     r0, #0x0b
 181        ldr     r1, REG_SDRAM_CONFIG2
 182        str     r0, [r1]
 183
 184        ldr     r3, VAL_SDRAM_CONFIG_SDF1
 185
 186skip_TMP_Patch:
 187
 188        /*
 189        * Delay for SDRAM initialization.
 190        */
 191        mov     r0,     #0x1800         /* value should be checked */
 1923:
 193        subs    r0,     r0,     #0x1    /* Decrement count */
 194        bne     3b
 195
 196        /*
 197         * Set SDRAM control values. Disable refresh before MRS command.
 198         */
 199
 200        /* mobile ddr operation */
 201        ldr     r0,     REG_SDRAM_OPERATION
 202        mov     r2,     #07
 203        str     r2,     [r0]
 204
 205        /* config register */
 206        ldr     r0,     REG_SDRAM_CONFIG
 207        str     r3,     [r0]
 208
 209        /* manual command register */
 210        ldr     r0,     REG_SDRAM_MANUAL_CMD
 211
 212        /* issue set cke high */
 213        mov     r1,     #CMD_SDRAM_CKE_SET_HIGH
 214        str     r1,     [r0]
 215
 216        /* issue nop */
 217        mov     r1,     #CMD_SDRAM_NOP
 218        str     r1,     [r0]
 219
 220        mov     r2,     #0x0100
 221waitMDDR1:
 222        subs    r2,     r2,      #1
 223        bne     waitMDDR1       /* delay loop */
 224
 225        /* issue precharge */
 226        mov     r1,     #CMD_SDRAM_PRECHARGE
 227        str     r1,     [r0]
 228
 229        /* issue autorefresh x 2 */
 230        mov     r1,     #CMD_SDRAM_AUTOREFRESH
 231        str     r1,     [r0]
 232        str     r1,     [r0]
 233
 234        /* mrs register ddr mobile */
 235        ldr     r0,     REG_SDRAM_MRS
 236        mov     r1,     #0x33
 237        str     r1,     [r0]
 238
 239        /* emrs1 low-power register */
 240        ldr     r0,     REG_SDRAM_EMRS1
 241        /* self refresh on all banks */
 242        mov     r1,     #0
 243        str     r1,     [r0]
 244
 245        ldr     r0,     REG_DLL_URD_CONTROL
 246        ldr     r1,     DLL_URD_CONTROL_VAL
 247        str     r1,     [r0]
 248
 249        ldr     r0,     REG_DLL_LRD_CONTROL
 250        ldr     r1,     DLL_LRD_CONTROL_VAL
 251        str     r1,     [r0]
 252
 253        ldr     r0,     REG_DLL_WRT_CONTROL
 254        ldr     r1,     DLL_WRT_CONTROL_VAL
 255        str     r1,     [r0]
 256
 257        /* delay loop */
 258        mov     r0,     #0x0100
 259waitMDDR2:
 260        subs    r0,     r0,     #1
 261        bne     waitMDDR2
 262
 263        /*
 264         * Delay for SDRAM initialization.
 265         */
 266        mov     r0,     #0x1800
 2674:
 268        subs    r0,     r0,     #1      /* Decrement count. */
 269        bne     4b
 270        b       common_tc
 271
 272skip_sdram:
 273        ldr     r0,     REG_SDRAM_CONFIG
 274        str     r3,     [r0]
 275
 276common_tc:
 277        /* slow interface */
 278        ldr     r1,     VAL_TC_EMIFS_CS0_CONFIG
 279        ldr     r0,     REG_TC_EMIFS_CS0_CONFIG
 280        str     r1,     [r0] /* Chip Select 0 */
 281
 282        ldr     r1,     VAL_TC_EMIFS_CS1_CONFIG
 283        ldr     r0,     REG_TC_EMIFS_CS1_CONFIG
 284        str     r1,     [r0] /* Chip Select 1 */
 285
 286        ldr     r1,     VAL_TC_EMIFS_CS3_CONFIG
 287        ldr     r0,     REG_TC_EMIFS_CS3_CONFIG
 288        str     r1,     [r0] /* Chip Select 3 */
 289
 290        ldr     r1,     VAL_TC_EMIFS_DWS
 291        ldr     r0,     REG_TC_EMIFS_DWS
 292        str     r1,     [r0] /* Enable EMIFS.RDY for CS1 (ether) */
 293
 294#ifdef CONFIG_H2_OMAP1610
 295        /* inserting additional 2 clock cycle hold time for LAN */
 296        ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
 297        ldr     r1,     VAL_TC_EMIFS_CS1_ADVANCED
 298        str     r1,     [r0]
 299#endif
 300        /* Start MPU Timer 1 */
 301        ldr     r0,     REG_MPU_LOAD_TIMER
 302        ldr     r1,     VAL_MPU_LOAD_TIMER
 303        str     r1,     [r0]
 304
 305        ldr     r0,     REG_MPU_CNTL_TIMER
 306        ldr     r1,     VAL_MPU_CNTL_TIMER
 307        str     r1,     [r0]
 308
 309        /*
 310         * Setup a temporary stack
 311         */
 312        ldr     sp,     SRAM_STACK
 313        bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 314
 315        /*
 316         * Save the old lr(passed in ip) and the current lr to stack
 317         */
 318        push    {ip, lr}
 319
 320        /*
 321         * go setup pll, mux, memory
 322         */
 323        bl      s_init
 324        pop     {ip, pc}
 325
 326        /* back to arch calling code */
 327        mov     pc,     lr
 328
 329        /* the literal pools origin */
 330        .ltorg
 331
 332REG_DEVICE_ID:                  /* 32 bits */
 333        .word 0xfffe2004
 334REG_TC_EMIFS_CONFIG:
 335        .word 0xfffecc0c
 336REG_TC_EMIFS_CS0_CONFIG:        /* 32 bits */
 337        .word 0xfffecc10
 338REG_TC_EMIFS_CS1_CONFIG:        /* 32 bits */
 339        .word 0xfffecc14
 340REG_TC_EMIFS_CS2_CONFIG:        /* 32 bits */
 341        .word 0xfffecc18
 342REG_TC_EMIFS_CS3_CONFIG:        /* 32 bits */
 343        .word 0xfffecc1c
 344REG_TC_EMIFS_DWS:               /* 32 bits */
 345        .word 0xfffecc40
 346#ifdef CONFIG_H2_OMAP1610
 347REG_TC_EMIFS_CS1_ADVANCED:      /* 32 bits */
 348        .word 0xfffecc54
 349#endif
 350
 351/* MPU clock/reset/power mode control registers */
 352REG_ARM_CKCTL:                  /* 16 bits */
 353        .word 0xfffece00
 354REG_ARM_IDLECT3:                /* 16 bits */
 355        .word 0xfffece24
 356REG_ARM_IDLECT2:                /* 16 bits */
 357        .word 0xfffece08
 358REG_ARM_IDLECT1:                /* 16 bits */
 359        .word 0xfffece04
 360REG_ARM_RSTCT2:                 /* 16 bits */
 361        .word 0xfffece14
 362REG_ARM_SYSST:                  /* 16 bits */
 363        .word 0xfffece18
 364
 365/* DPLL control registers */
 366REG_DPLL1_CTL:                  /* 16 bits */
 367        .word 0xfffecf00
 368
 369/* Watch Dog register */
 370/* secure watchdog stop */
 371REG_WSPRDOG:
 372        .word 0xfffeb048
 373/* watchdog write pending */
 374REG_WWPSDOG:
 375        .word 0xfffeb034
 376
 377WSPRDOG_VAL1:
 378        .word 0x0000aaaa
 379WSPRDOG_VAL2:
 380        .word 0x00005555
 381
 382/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
 383 counter @8192 rows, 10 ns, 8 burst */
 384REG_SDRAM_CONFIG:
 385        .word 0xfffecc20
 386REG_SDRAM_CONFIG2:
 387        .word 0xfffecc3c
 388REG_TC_EMIFF_DOUBLER:           /* 32 bits */
 389        .word 0xfffecc60
 390
 391/* Operation register */
 392REG_SDRAM_OPERATION:
 393        .word 0xfffecc80
 394
 395/* Manual command register */
 396REG_SDRAM_MANUAL_CMD:
 397        .word 0xfffecc84
 398
 399/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
 400REG_SDRAM_MRS:
 401        .word 0xfffecc70
 402
 403/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
 404REG_SDRAM_EMRS1:
 405        .word 0xfffecc78
 406
 407/* WRT DLL register */
 408REG_DLL_WRT_CONTROL:
 409        .word 0xfffecc68
 410DLL_WRT_CONTROL_VAL:
 411        .word 0x03f00002    /* Phase of 72deg, write offset +31  */
 412
 413/* URD DLL register */
 414REG_DLL_URD_CONTROL:
 415        .word 0xfffeccc0
 416DLL_URD_CONTROL_VAL:
 417        .word 0x00800002    /* Phase of 72deg, read offset +31  */
 418
 419/* LRD DLL register */
 420REG_DLL_LRD_CONTROL:
 421        .word 0xfffecccc
 422DLL_LRD_CONTROL_VAL:
 423        .word 0x00800002    /* read offset +31  */
 424
 425REG_WATCHDOG:
 426        .word 0xfffec808
 427WATCHDOG_VAL1:
 428        .word 0x000000f5
 429WATCHDOG_VAL2:
 430        .word 0x000000a0
 431
 432REG_MPU_LOAD_TIMER:
 433        .word 0xfffec504
 434REG_MPU_CNTL_TIMER:
 435        .word 0xfffec500
 436VAL_MPU_LOAD_TIMER:
 437        .word 0xffffffff
 438VAL_MPU_CNTL_TIMER:
 439        .word 0xffffffa1
 440
 441/* 96 MHz Samsung Mobile DDR */
 442/* Original setting for TMX device */
 443VAL_SDRAM_CONFIG_SDF0:
 444    .word 0x0014e6fe
 445
 446/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
 447VAL_SDRAM_CONFIG_SDF1:
 448    .word 0x0114e6fe
 449
 450VAL_ARM_CKCTL:
 451        .word 0x2000            /* was: 0x3000, now use CLK_REF for timer input */
 452VAL_DPLL1_CTL:
 453        .word 0x2830
 454
 455#ifdef CONFIG_OSK_OMAP5912
 456VAL_TC_EMIFS_CS0_CONFIG:
 457        .word 0x002130b0
 458VAL_TC_EMIFS_CS1_CONFIG:
 459        .word 0x00001133
 460VAL_TC_EMIFS_CS2_CONFIG:
 461        .word 0x000055f0
 462VAL_TC_EMIFS_CS3_CONFIG:
 463        .word 0x88013141
 464VAL_TC_EMIFS_DWS:       /* Enable EMIFS.RDY for CS1 access (ether) */
 465        .word 0x000000c0
 466VAL_DEVICE_ID_TMP:      /* TMP/TMS=0xb65f, TMX=0xb58c */
 467        .word 0xb65f
 468#endif
 469
 470#ifdef CONFIG_H2_OMAP1610
 471VAL_TC_EMIFS_CS0_CONFIG:
 472        .word 0x00203331
 473VAL_TC_EMIFS_CS1_CONFIG:
 474        .word 0x8180fff3
 475VAL_TC_EMIFS_CS2_CONFIG:
 476        .word 0xf800f22a
 477VAL_TC_EMIFS_CS3_CONFIG:
 478        .word 0x88013141
 479VAL_TC_EMIFS_CS1_ADVANCED:
 480        .word 0x00000022
 481#endif
 482
 483VAL_ARM_IDLECT1:
 484        .word 0x00000400
 485VAL_ARM_IDLECT2:
 486        .word 0x00000886
 487VAL_ARM_IDLECT3:
 488        .word 0x00000015
 489
 490SRAM_STACK:
 491        .word CONFIG_SYS_INIT_SP_ADDR
 492
 493/* command values */
 494.equ CMD_SDRAM_NOP,             0x00000000
 495.equ CMD_SDRAM_PRECHARGE,       0x00000001
 496.equ CMD_SDRAM_AUTOREFRESH,     0x00000002
 497.equ CMD_SDRAM_CKE_SET_HIGH,    0x00000007
 498