1/* 2 * Copyright (C) ST-Ericsson SA 2009 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23#ifndef _U8500_I2C_H_ 24#define _U8500_I2C_H_ 25 26#include <asm/types.h> 27#include <asm/io.h> 28#include <asm/errno.h> 29#include <asm/arch/u8500.h> 30 31struct u8500_i2c_regs { 32 u32 cr; /* Control Register 0x00 */ 33 u32 scr; /* Slave Address Register 0x04 */ 34 u32 hsmcr; /* HS Master code Register 0x08 */ 35 u32 mcr; /* Master Control Register 0x0C */ 36 u32 tfr; /* Transmit Fifo Register 0x10 */ 37 u32 sr; /* Status Register 0x14 */ 38 u32 rfr; /* Receiver Fifo Register 0x18 */ 39 u32 tftr; /* Transmit Fifo Threshold Register 0x1C */ 40 u32 rftr; /* Receiver Fifo Threshold Register 0x20 */ 41 u32 dmar; /* DMA register 0x24 */ 42 u32 brcr; /* Baud Rate Counter Register 0x28 */ 43 u32 imscr; /* Interrupt Mask Set and Clear Register 0x2C */ 44 u32 risr; /* Raw interrupt status register 0x30 */ 45 u32 misr; /* Masked interrupt status register 0x34 */ 46 u32 icr; /* Interrupt Set and Clear Register 0x38 */ 47 u32 reserved_1[(0xFE0 - 0x3c) >> 2]; /* Reserved 0x03C to 0xFE0 */ 48 u32 periph_id_0; /* peripheral ID 0 0xFE0 */ 49 u32 periph_id_1; /* peripheral ID 1 0xFE4 */ 50 u32 periph_id_2; /* peripheral ID 2 0xFE8 */ 51 u32 periph_id_3; /* peripheral ID 3 0xFEC */ 52 u32 cell_id_0; /* I2C cell ID 0 0xFF0 */ 53 u32 cell_id_1; /* I2C cell ID 1 0xFF4 */ 54 u32 cell_id_2; /* I2C cell ID 2 0xFF8 */ 55 u32 cell_id_3; /* I2C cell ID 3 0xFFC */ 56}; 57 58 59/* Control Register */ 60 61/* Mask values for control register mask */ 62#define U8500_I2C_CR_PE 0x0001 /* Peripheral enable */ 63#define U8500_I2C_CR_OM 0x0006 /* Operation mode */ 64#define U8500_I2C_CR_SAM 0x0008 /* Slave Addressing mode */ 65#define U8500_I2C_CR_SM 0x0030 /* Speed mode */ 66#define U8500_I2C_CR_SGCM 0x0040 /* Slave General call mode */ 67#define U8500_I2C_CR_FTX 0x0080 /* Flush Transmit */ 68#define U8500_I2C_CR_FRX 0x0100 /* Flush Receive */ 69#define U8500_I2C_CR_DMA_TX_EN 0x0200 /* DMA TX Enable */ 70#define U8500_I2C_CR_DMA_RX_EN 0x0400 /* DMA Rx Enable */ 71#define U8500_I2C_CR_DMA_SLE 0x0800 /* DMA Synchronization Logic enable */ 72#define U8500_I2C_CR_LM 0x1000 /* Loop back mode */ 73#define U8500_I2C_CR_FON 0x6000 /* Filtering On */ 74 75/* shift valus for control register bit fields */ 76#define U8500_I2C_CR_SHIFT_PE 0 /* Peripheral enable */ 77#define U8500_I2C_CR_SHIFT_OM 1 /* Operation mode */ 78#define U8500_I2C_CR_SHIFT_SAM 3 /* Slave Addressing mode */ 79#define U8500_I2C_CR_SHIFT_SM 4 /* Speed mode */ 80#define U8500_I2C_CR_SHIFT_SGCM 6 /* Slave General call mode */ 81#define U8500_I2C_CR_SHIFT_FTX 7 /* Flush Transmit */ 82#define U8500_I2C_CR_SHIFT_FRX 8 /* Flush Receive */ 83#define U8500_I2C_CR_SHIFT_DMA_TX_EN 9 /* DMA TX Enable */ 84#define U8500_I2C_CR_SHIFT_DMA_RX_EN 10 /* DMA Rx Enable */ 85#define U8500_I2C_CR_SHIFT_DMA_SLE 11 /* DMA Synch Logic enable */ 86#define U8500_I2C_CR_SHIFT_LM 12 /* Loop back mode */ 87#define U8500_I2C_CR_SHIFT_FON 13 /* Filtering On */ 88 89/* bus operation modes */ 90#define U8500_I2C_BUS_SLAVE_MODE 0 91#define U8500_I2C_BUS_MASTER_MODE 1 92#define U8500_I2C_BUS_MASTER_SLAVE_MODE 2 93 94 95/* Slave control register*/ 96 97/* Mask values slave control register */ 98#define U8500_I2C_SCR_ADDR 0x3FF 99#define U8500_I2C_SCR_DATA_SETUP_TIME 0xFFFF0000 100 101/* Shift values for Slave control register */ 102#define U8500_I2C_SCR_SHIFT_ADDR 0 103#define U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME 16 104 105 106/* Master Control Register */ 107 108/* Mask values for Master control register */ 109#define U8500_I2C_MCR_OP 0x00000001 /* Operation */ 110#define U8500_I2C_MCR_A7 0x000000FE /* LSB bits of Address */ 111#define U8500_I2C_MCR_EA10 0x00000700 /* Extended Address */ 112#define U8500_I2C_MCR_SB 0x00000800 /* Start byte procedure */ 113#define U8500_I2C_MCR_AM 0x00003000 /* Address type */ 114#define U8500_I2C_MCR_STOP 0x00004000 /* stop condition */ 115#define U8500_I2C_MCR_LENGTH 0x03FF8000 /* Frame length */ 116#define U8500_I2C_MCR_A10 0x000007FE /* Enable 10 bit address */ 117/* mask for length field,stop and operation */ 118#define U8500_I2C_MCR_LENGTH_STOP_OP 0x3FFC001 119 120/* Shift values for Master control values */ 121#define U8500_I2C_MCR_SHIFT_OP 0 /* Operation */ 122#define U8500_I2C_MCR_SHIFT_A7 1 /* LSB bits of Address */ 123#define U8500_I2C_MCR_SHIFT_EA10 8 /* Extended Address */ 124#define U8500_I2C_MCR_SHIFT_SB 11 /* Start byte procedure */ 125#define U8500_I2C_MCR_SHIFT_AM 12 /* Address type */ 126#define U8500_I2C_MCR_SHIFT_STOP 14 /* stop condition */ 127#define U8500_I2C_MCR_SHIFT_LENGTH 15 /* Frame length */ 128#define U8500_I2C_MCR_SHIFT_A10 1 /* Enable 10 bit address */ 129 130#define U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP 0 131 132 133/* Status Register */ 134 135/* Mask values for Status register */ 136#define U8500_I2C_SR_OP 0x00000003 /* Operation */ 137#define U8500_I2C_SR_STATUS 0x0000000C /* Controller Status */ 138#define U8500_I2C_SR_CAUSE 0x00000070 /* Abort Cause */ 139#define U8500_I2C_SR_TYPE 0x00000180 /* Receive Type */ 140#define U8500_I2C_SR_LENGTH 0x000FF700 /* Transfer length */ 141 142/* Shift values for Status register */ 143#define U8500_I2C_SR_SHIFT_OP 0 /* Operation */ 144#define U8500_I2C_SR_SHIFT_STATUS 2 /* Controller Status */ 145#define U8500_I2C_SR_SHIFT_CAUSE 4 /* Abort Cause */ 146#define U8500_I2C_SR_SHIFT_TYPE 7 /* Receive Type */ 147#define U8500_I2C_SR_SHIFT_LENGTH 9 /* Transfer length */ 148 149/* abort cause */ 150#define U8500_I2C_NACK_ADDR 0 151#define U8500_I2C_NACK_DATA 1 152#define U8500_I2C_ACK_MCODE 2 153#define U8500_I2C_ARB_LOST 3 154#define U8500_I2C_BERR_START 4 155#define U8500_I2C_BERR_STOP 5 156#define U8500_I2C_OVFL 6 157 158 159/* Baud rate counter registers */ 160 161/* Mask values for Baud rate counter register */ 162#define U8500_I2C_BRCR_BRCNT2 0xFFFF /* Baud Rate Cntr BRCR for HS */ 163#define U8500_I2C_BRCR_BRCNT1 0xFFFF0000 /* BRCR for Standard and Fast */ 164 165/* Shift values for the Baud rate counter register */ 166#define U8500_I2C_BRCR_SHIFT_BRCNT2 0 167#define U8500_I2C_BRCR_SHIFT_BRCNT1 16 168 169 170/* Interrupt Register */ 171 172/* Mask values for Interrupt registers */ 173#define U8500_I2C_INT_TXFE 0x00000001 /* Tx fifo empty */ 174#define U8500_I2C_INT_TXFNE 0x00000002 /* Tx Fifo nearly empty */ 175#define U8500_I2C_INT_TXFF 0x00000004 /* Tx Fifo Full */ 176#define U8500_I2C_INT_TXFOVR 0x00000008 /* Tx Fifo over run */ 177#define U8500_I2C_INT_RXFE 0x00000010 /* Rx Fifo Empty */ 178#define U8500_I2C_INT_RXFNF 0x00000020 /* Rx Fifo nearly empty */ 179#define U8500_I2C_INT_RXFF 0x00000040 /* Rx Fifo Full */ 180#define U8500_I2C_INT_RFSR 0x00010000 /* Read From slave request */ 181#define U8500_I2C_INT_RFSE 0x00020000 /* Read from slave empty */ 182#define U8500_I2C_INT_WTSR 0x00040000 /* Write to Slave request */ 183#define U8500_I2C_INT_MTD 0x00080000 /* Master Transcation Done*/ 184#define U8500_I2C_INT_STD 0x00100000 /* Slave Transaction Done */ 185#define U8500_I2C_INT_MAL 0x01000000 /* Master Arbitation Lost */ 186#define U8500_I2C_INT_BERR 0x02000000 /* Bus Error */ 187#define U8500_I2C_INT_MTDWS 0x10000000 /* Master Tran Done wo/ Stop */ 188 189/* Max clocks (Hz) */ 190#define U8500_I2C_MAX_STANDARD_SCL 100000 191#define U8500_I2C_MAX_FAST_SCL 400000 192#define U8500_I2C_MAX_HIGH_SPEED_SCL 3400000 193 194#endif /* _U8500_I2C_H_ */ 195