1/* 2 * (C) Copyright 2002 ELTEC Elektronik AG 3 * Frank Gottschling <fgottschling@eltec.de> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#define GTREGREAD(x) 0xffffffff /* needed for debug */ 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 38#define CONFIG_SYS_TEXT_BASE 0xFFF00000 39 40/* these hardware addresses are pretty bogus, please change them to 41 suit your needs */ 42 43/* first ethernet */ 44#define CONFIG_ETHADDR 00:00:5b:ee:de:ad 45 46#define CONFIG_IPADDR 192.168.0.105 47#define CONFIG_SERVERIP 192.168.0.100 48 49#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */ 50 51#define CONFIG_BAUDRATE 9600 /* console baudrate */ 52 53#undef CONFIG_WATCHDOG 54 55#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 56 57#define CONFIG_ZERO_BOOTDELAY_CHECK 58 59#undef CONFIG_BOOTARGS 60#define CONFIG_BOOTCOMMAND \ 61 "bootp 1000000; " \ 62 "setenv bootargs root=ramfs console=ttyS00,9600 " \ 63 "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \ 64 "${netmask}:${hostname}:eth0:none; " \ 65 "bootm" 66 67#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 68#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ 69 70/* 71 * BOOTP options 72 */ 73#define CONFIG_BOOTP_SUBNETMASK 74#define CONFIG_BOOTP_GATEWAY 75#define CONFIG_BOOTP_HOSTNAME 76#define CONFIG_BOOTP_BOOTPATH 77 78#define CONFIG_BOOTP_BOOTFILESIZE 79 80 81/* 82 * Command line configuration. 83 */ 84#include <config_cmd_default.h> 85 86#define CONFIG_CMD_PCI 87#define CONFIG_CMD_JFFS2 88 89 90/* 91 * Miscellaneous configurable options 92 */ 93#define CONFIG_SYS_LONGHELP /* undef to save memory */ 94#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 95 96/* 97 * choose between COM1 and COM2 as serial console 98 */ 99#define CONFIG_CONS_INDEX 1 100 101#if defined(CONFIG_CMD_KGDB) 102#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 103#else 104#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 105#endif 106#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 107#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 108#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 109 110#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 111#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ 112 113#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 114 115#define CONFIG_SYS_HZ 1000 /* dec. freq: 1 ms ticks */ 116 117#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 118 119/* 120 * Low Level Configuration Settings 121 * (address mappings, register initial values, etc.) 122 * You should know what you are doing if you make changes here. 123 */ 124#define CONFIG_SYS_BOARD_ASM_INIT 125#define CONFIG_MISC_INIT_R 126 127/* 128 * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP) 129 */ 130#undef CONFIG_SYS_ADDRESS_MAP_A 131 132#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 133#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 134#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000 135 136#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 137#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000 138#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000 139 140#define CONFIG_SYS_ISA_MEM_BUS 0x00000000 141#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000 142#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000 143 144#define CONFIG_SYS_PCI_IO_BUS 0x00800000 145#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000 146#define CONFIG_SYS_PCI_IO_SIZE 0x00400000 147 148#define CONFIG_SYS_ISA_IO_BUS 0x00000000 149#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000 150#define CONFIG_SYS_ISA_IO_SIZE 0x00800000 151 152/* driver defines FDC,IDE,... */ 153#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS 154#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS 155#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS 156 157/* 158 * Start addresses for the final memory configuration 159 * (Set up by the startup code) 160 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 161 */ 162#define CONFIG_SYS_SDRAM_BASE 0x00000000 163 164#define CONFIG_SYS_USR_LED_BASE 0x78000000 165#define CONFIG_SYS_NVRAM_BASE 0xff000000 166#define CONFIG_SYS_UART_BASE 0xff400000 167#define CONFIG_SYS_FLASH_BASE 0xfff00000 168 169#define MPC107_EUMB_ADDR 0xfce00000 170#define MPC107_EUMB_PI 0xfce41090 171#define MPC107_EUMB_GCR 0xfce41020 172#define MPC107_EUMB_IACKR 0xfce600a0 173#define MPC107_I2C_ADDR 0xfce03000 174 175/* 176 * Definitions for initial stack pointer and data area 177 */ 178#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ 179#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 180#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 181#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 182 183/* 184 * Flash mapping/organization on the MPC10x. 185 */ 186#define FLASH_BASE0_PRELIM 0xff800000 187#define FLASH_BASE1_PRELIM 0xffc00000 188 189#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 190#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 191 192#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 193#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 194 195/* 196 * JFFS2 partitions 197 * 198 */ 199/* No command line, one static partition, whole device */ 200#undef CONFIG_CMD_MTDPARTS 201#define CONFIG_JFFS2_DEV "nor0" 202#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 203#define CONFIG_JFFS2_PART_OFFSET 0x00000000 204 205/* mtdparts command line support */ 206/* Note: fake mtd_id used, no linux mtd map file */ 207/* 208#define CONFIG_CMD_MTDPARTS 209#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1" 210#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)" 211*/ 212 213#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 214#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ 215#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ 216#undef CONFIG_SYS_MEMTEST 217 218/* 219 * Environment settings 220 */ 221#define CONFIG_ENV_OVERWRITE 222#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ 223#define CONFIG_SYS_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */ 224#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ 225#define CONFIG_ENV_ADDR 0x0 226#define CONFIG_ENV_MAP_ADRS 0xff000000 227#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 228#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */ 229#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ 230 231/* 232 * Serial devices 233 */ 234#define CONFIG_SYS_NS16550 235#define CONFIG_SYS_NS16550_SERIAL 236#define CONFIG_SYS_NS16550_REG_SIZE 1 237#define CONFIG_SYS_NS16550_CLK 24000000 238#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0) 239#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_UART_BASE + 8) 240 241/* 242 * PCI stuff 243 */ 244#define CONFIG_PCI /* include pci support */ 245#define CONFIG_PCI_PNP /* pci plug-and-play */ 246#define CONFIG_PCI_HOST PCI_HOST_AUTO 247#undef CONFIG_PCI_SCAN_SHOW 248 249/* 250 * Optional Video console (graphic: SMI LynxEM) 251 */ 252#define CONFIG_VIDEO 253#define CONFIG_CFB_CONSOLE 254#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10)) 255#define VIDEO_TSTC_FCT serial_tstc 256#define VIDEO_GETC_FCT serial_getc 257 258#define CONFIG_VIDEO_SMI_LYNXEM 259#define CONFIG_VIDEO_LOGO 260#define CONFIG_CONSOLE_EXTRA_INFO 261 262/* 263 * Initial BATs 264 */ 265#if 1 266 267#define CONFIG_SYS_IBAT0L 0 268#define CONFIG_SYS_IBAT0U 0 269#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L 270#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U 271 272#define CONFIG_SYS_IBAT1L 0 273#define CONFIG_SYS_IBAT1U 0 274#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 275#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 276 277#define CONFIG_SYS_IBAT2L 0 278#define CONFIG_SYS_IBAT2U 0 279#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 280#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 281 282#define CONFIG_SYS_IBAT3L 0 283#define CONFIG_SYS_IBAT3U 0 284#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 285#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 286 287#else 288 289/* SDRAM */ 290#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW) 291#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 292#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L 293#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U 294 295/* address range for flashes */ 296#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) 297#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) 298#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 299#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 300 301/* ISA IO space */ 302#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) 303#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) 304#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 305#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 306 307/* ISA memory space */ 308#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) 309#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) 310#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 311#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 312 313#endif 314 315/* 316 * Speed settings are board specific 317 */ 318#define CONFIG_SYS_BUS_CLK 100000000 319#define CONFIG_SYS_CPU_CLK 400000000 320 321/* 322 * For booting Linux, the board info and command line data 323 * have to be in the first 8 MB of memory, since this is 324 * the maximum mapped by the Linux kernel during initialization. 325 */ 326#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 327 328/* 329 * Cache Configuration 330 */ 331#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ 332#if defined(CONFIG_CMD_KGDB) 333#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 334#endif 335 336/* 337 * L2CR setup -- make sure this is right for your board! 338 * look in include/74xx_7xx.h for the defines used here 339 */ 340 341#define CONFIG_SYS_L2 342 343#if 1 344#define L2_INIT 0 /* cpu 750 CXe*/ 345#else 346#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ 347 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) 348#endif 349#define L2_ENABLE (L2_INIT | L2CR_L2E) 350 351#define CONFIG_EEPRO100 352#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 353#define CONFIG_EEPRO100_SROM_WRITE 354 355#endif /* __CONFIG_H */ 356