1/* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr 26 * U-Boot port on NetTA4 board 27 */ 28 29#ifndef __CONFIG_H 30#define __CONFIG_H 31 32#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2 33#error Unsupported CONFIG_NETTA2 version 34#endif 35 36/* 37 * High Level Configuration Options 38 * (easy to change) 39 */ 40 41#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ 42#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */ 43 44#define CONFIG_SYS_TEXT_BASE 0x40000000 45 46#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 47#undef CONFIG_8xx_CONS_SMC2 48#undef CONFIG_8xx_CONS_NONE 49 50#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 51 52/* #define CONFIG_XIN 10000000 */ 53#define CONFIG_XIN 50000000 54/* #define MPC8XX_HZ 120000000 */ 55#define MPC8XX_HZ 66666666 56 57#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ 58 59#if 0 60#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 61#else 62#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 63#endif 64 65#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ 66 67#define CONFIG_PREBOOT "echo;" 68 69#undef CONFIG_BOOTARGS 70#define CONFIG_BOOTCOMMAND \ 71 "tftpboot; " \ 72 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 73 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 74 "bootm" 75 76#define CONFIG_SOURCE 77#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 78#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 79 80#undef CONFIG_WATCHDOG /* watchdog disabled */ 81 82#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 83 84#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 85#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ 86 87/* 88 * BOOTP options 89 */ 90#define CONFIG_BOOTP_SUBNETMASK 91#define CONFIG_BOOTP_GATEWAY 92#define CONFIG_BOOTP_HOSTNAME 93#define CONFIG_BOOTP_BOOTPATH 94#define CONFIG_BOOTP_BOOTFILESIZE 95#define CONFIG_BOOTP_NISDOMAIN 96 97 98#undef CONFIG_MAC_PARTITION 99#undef CONFIG_DOS_PARTITION 100 101#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 102 103#define FEC_ENET 1 /* eth.c needs it that way... */ 104#undef CONFIG_SYS_DISCOVER_PHY 105#define CONFIG_MII 1 106#define CONFIG_MII_INIT 1 107#define CONFIG_RMII 1 /* use RMII interface */ 108 109#define CONFIG_ETHER_ON_FEC1 1 110#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ 111#define CONFIG_FEC1_PHY_NORXERR 1 112 113#define CONFIG_ETHER_ON_FEC2 1 114#define CONFIG_FEC2_PHY 4 115#define CONFIG_FEC2_PHY_NORXERR 1 116 117#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ 118 119 120/* 121 * Command line configuration. 122 */ 123#include <config_cmd_default.h> 124 125#define CONFIG_CMD_DHCP 126#define CONFIG_CMD_PING 127#define CONFIG_CMD_MII 128#define CONFIG_CMD_CDP 129 130 131#define CONFIG_BOARD_EARLY_INIT_F 1 132#define CONFIG_MISC_INIT_R 133 134/* 135 * Miscellaneous configurable options 136 */ 137#define CONFIG_SYS_LONGHELP /* undef to save memory */ 138#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 139 140#define CONFIG_SYS_HUSH_PARSER 1 141 142#if defined(CONFIG_CMD_KGDB) 143#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 144#else 145#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 146#endif 147#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 148#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 149#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 150 151#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ 152#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ 153 154#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 155 156#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 157 158/* 159 * Low Level Configuration Settings 160 * (address mappings, register initial values, etc.) 161 * You should know what you are doing if you make changes here. 162 */ 163/*----------------------------------------------------------------------- 164 * Internal Memory Mapped Register 165 */ 166#define CONFIG_SYS_IMMR 0xFF000000 167 168/*----------------------------------------------------------------------- 169 * Definitions for initial stack pointer and data area (in DPRAM) 170 */ 171#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 172#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ 173#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 174#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 175 176/*----------------------------------------------------------------------- 177 * Start addresses for the final memory configuration 178 * (Set up by the startup code) 179 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 180 */ 181#define CONFIG_SYS_SDRAM_BASE 0x00000000 182#define CONFIG_SYS_FLASH_BASE 0x40000000 183#if defined(DEBUG) 184#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 185#else 186#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 187#endif 188#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 189#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 190#if CONFIG_NETTA2_VERSION == 2 191#define CONFIG_SYS_FLASH_BASE4 0x40080000 192#endif 193 194#define CONFIG_SYS_RESET_ADDRESS 0x80000000 195 196/* 197 * For booting Linux, the board info and command line data 198 * have to be in the first 8 MB of memory, since this is 199 * the maximum mapped by the Linux kernel during initialization. 200 */ 201#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 202 203/*----------------------------------------------------------------------- 204 * FLASH organization 205 */ 206#if CONFIG_NETTA2_VERSION == 1 207#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 208#elif CONFIG_NETTA2_VERSION == 2 209#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 210#endif 211#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ 212 213#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 214#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 215 216#define CONFIG_ENV_IS_IN_FLASH 1 217#define CONFIG_ENV_SECT_SIZE 0x10000 218 219#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) 220#define CONFIG_ENV_OFFSET 0 221#define CONFIG_ENV_SIZE 0x4000 222 223#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) 224#define CONFIG_ENV_OFFSET_REDUND 0 225#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 226 227/*----------------------------------------------------------------------- 228 * Cache Configuration 229 */ 230#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 231#if defined(CONFIG_CMD_KGDB) 232#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 233#endif 234 235/*----------------------------------------------------------------------- 236 * SYPCR - System Protection Control 11-9 237 * SYPCR can only be written once after reset! 238 *----------------------------------------------------------------------- 239 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 240 */ 241#if defined(CONFIG_WATCHDOG) 242#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 243 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 244#else 245#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 246#endif 247 248/*----------------------------------------------------------------------- 249 * SIUMCR - SIU Module Configuration 11-6 250 *----------------------------------------------------------------------- 251 * PCMCIA config., multi-function pin tri-state 252 */ 253#ifndef CONFIG_CAN_DRIVER 254#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) 255#else /* we must activate GPL5 in the SIUMCR for CAN */ 256#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) 257#endif /* CONFIG_CAN_DRIVER */ 258 259/*----------------------------------------------------------------------- 260 * TBSCR - Time Base Status and Control 11-26 261 *----------------------------------------------------------------------- 262 * Clear Reference Interrupt Status, Timebase freezing enabled 263 */ 264#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 265 266/*----------------------------------------------------------------------- 267 * RTCSC - Real-Time Clock Status and Control Register 11-27 268 *----------------------------------------------------------------------- 269 */ 270#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 271 272/*----------------------------------------------------------------------- 273 * PISCR - Periodic Interrupt Status and Control 11-31 274 *----------------------------------------------------------------------- 275 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 276 */ 277#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 278 279/*----------------------------------------------------------------------- 280 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 281 *----------------------------------------------------------------------- 282 * Reset PLL lock status sticky bit, timer expired status bit and timer 283 * interrupt status bit 284 * 285 */ 286 287#if CONFIG_XIN == 10000000 288 289#if MPC8XX_HZ == 120000000 290#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 291 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ 292 PLPRCR_TEXPS) 293#elif MPC8XX_HZ == 100000000 294#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 295 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ 296 PLPRCR_TEXPS) 297#elif MPC8XX_HZ == 50000000 298#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 299 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ 300 PLPRCR_TEXPS) 301#elif MPC8XX_HZ == 25000000 302#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 303 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ 304 PLPRCR_TEXPS) 305#elif MPC8XX_HZ == 40000000 306#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 307 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ 308 PLPRCR_TEXPS) 309#elif MPC8XX_HZ == 75000000 310#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 311 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ 312 PLPRCR_TEXPS) 313#else 314#error unsupported CPU freq for XIN = 10MHz 315#endif 316 317#elif CONFIG_XIN == 50000000 318 319#if MPC8XX_HZ == 120000000 320#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 321 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ 322 PLPRCR_TEXPS) 323#elif MPC8XX_HZ == 100000000 324#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 325 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ 326 PLPRCR_TEXPS) 327#elif MPC8XX_HZ == 66666666 328#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 329 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ 330 PLPRCR_TEXPS) 331#else 332#error unsupported CPU freq for XIN = 50MHz 333#endif 334 335#else 336 337#error unsupported XIN freq 338#endif 339 340 341/* 342 *----------------------------------------------------------------------- 343 * SCCR - System Clock and reset Control Register 15-27 344 *----------------------------------------------------------------------- 345 * Set clock output, timebase and RTC source and divider, 346 * power management and some other internal clocks 347 * 348 * Note: When TBS == 0 the timebase is independent of current cpu clock. 349 */ 350 351#define SCCR_MASK SCCR_EBDF11 352#if MPC8XX_HZ > 66666666 353#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ 354 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 355 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 356 SCCR_DFALCD00 | SCCR_EBDF01) 357#else 358#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ 359 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 360 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 361 SCCR_DFALCD00) 362#endif 363 364/*----------------------------------------------------------------------- 365 * 366 *----------------------------------------------------------------------- 367 * 368 */ 369/*#define CONFIG_SYS_DER 0x2002000F*/ 370#define CONFIG_SYS_DER 0 371 372/* 373 * Init Memory Controller: 374 * 375 * BR0/1 and OR0/1 (FLASH) 376 */ 377 378#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 379 380/* used to re-map FLASH both when starting from SRAM or FLASH: 381 * restrict access enough to keep SRAM working (if any) 382 * but not too much to meddle with FLASH accesses 383 */ 384#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 385#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 386 387/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ 388#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) 389 390#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 391#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 392#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) 393 394#if CONFIG_NETTA2_VERSION == 2 395 396#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ 397 398#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 399#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 400#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) 401 402#endif 403 404/* 405 * BR3 and OR3 (SDRAM) 406 * 407 */ 408#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ 409#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ 410 411/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 412#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) 413 414#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) 415#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) 416 417/* 418 * Memory Periodic Timer Prescaler 419 */ 420 421/* 422 * Memory Periodic Timer Prescaler 423 * 424 * The Divider for PTA (refresh timer) configuration is based on an 425 * example SDRAM configuration (64 MBit, one bank). The adjustment to 426 * the number of chip selects (NCS) and the actually needed refresh 427 * rate is done by setting MPTPR. 428 * 429 * PTA is calculated from 430 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 431 * 432 * gclk CPU clock (not bus clock!) 433 * Trefresh Refresh cycle * 4 (four word bursts used) 434 * 435 * 4096 Rows from SDRAM example configuration 436 * 1000 factor s -> ms 437 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 438 * 4 Number of refresh cycles per period 439 * 64 Refresh cycle in ms per number of rows 440 * -------------------------------------------- 441 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 442 * 443 * 50 MHz => 50.000.000 / Divider = 98 444 * 66 Mhz => 66.000.000 / Divider = 129 445 * 80 Mhz => 80.000.000 / Divider = 156 446 */ 447 448#define CONFIG_SYS_MAMR_PTA 234 449 450/* 451 * For 16 MBit, refresh rates could be 31.3 us 452 * (= 64 ms / 2K = 125 / quad bursts). 453 * For a simpler initialization, 15.6 us is used instead. 454 * 455 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 456 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 457 */ 458#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 459#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 460 461/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 462#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 463#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 464 465/* 466 * MAMR settings for SDRAM 467 */ 468 469/* 8 column SDRAM */ 470#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 471 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 472 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 473 474/* 9 column SDRAM */ 475#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 476 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 477 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 478 479#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ 480 481/****************************************************************/ 482 483#define DSP_SIZE 0x00010000 /* 64K */ 484#define NAND_SIZE 0x00010000 /* 64K */ 485 486#define DSP_BASE 0xF1000000 487#define NAND_BASE 0xF1010000 488 489/*****************************************************************************/ 490 491#define CONFIG_SYS_DIRECT_FLASH_TFTP 492 493/*****************************************************************************/ 494 495#if CONFIG_NETTA2_VERSION == 1 496#define STATUS_LED_BIT 0x00000008 /* bit 28 */ 497#elif CONFIG_NETTA2_VERSION == 2 498#define STATUS_LED_BIT 0x00000080 /* bit 24 */ 499#endif 500 501#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 502#define STATUS_LED_STATE STATUS_LED_BLINKING 503 504#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ 505#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ 506 507#ifndef __ASSEMBLY__ 508 509/* LEDs */ 510 511/* led_id_t is unsigned int mask */ 512typedef unsigned int led_id_t; 513 514#define __led_toggle(_msk) \ 515 do { \ 516 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \ 517 } while(0) 518 519#define __led_set(_msk, _st) \ 520 do { \ 521 if ((_st)) \ 522 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \ 523 else \ 524 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ 525 } while(0) 526 527#define __led_init(msk, st) __led_set(msk, st) 528 529#endif 530 531/*********************************************************************************************************** 532 533 ---------------------------------------------------------------------------------------------- 534 535 (V1) version 1 of the board 536 (V2) version 2 of the board 537 538 ---------------------------------------------------------------------------------------------- 539 540 Pin definitions: 541 542 +------+----------------+--------+------------------------------------------------------------ 543 | # | Name | Type | Comment 544 +------+----------------+--------+------------------------------------------------------------ 545 | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select 546 | PA7 | DSP_INT | Output | DSP interrupt 547 | PA10 | DSP_RESET | Output | DSP reset 548 | PA14 | USBOE | Output | USB (1) 549 | PA15 | USBRXD | Output | USB (1) 550 | PB19 | BT_RTS | Output | Bluetooth (0) 551 | PB23 | BT_CTS | Output | Bluetooth (0) 552 | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select 553 | PB27 | SPICS_DISP | Output | Display chip select 554 | PB28 | SPI_RXD_3V | Input | SPI Data Rx 555 | PB29 | SPI_TXD | Output | SPI Data Tx 556 | PB30 | SPI_CLK | Output | SPI Clock 557 | PC10 | DISPA0 | Output | Display A0 558 | PC11 | BACKLIGHT | Output | Display backlit 559 | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD 560 | | IO_RESET | Output | (V2) General I/O reset 561 | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) 562 | | HOOK | Input | (V2) Hook input interrupt 563 | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK 564 | | F_RY_BY | Input | (V2) NAND F_RY_BY 565 | PE17 | F_ALE | Output | NAND F_ALE 566 | PE18 | F_CLE | Output | NAND F_CLE 567 | PE20 | F_CE | Output | NAND F_CE 568 | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select 569 | | LED | Output | (V2) LED 570 | PE27 | SPICS_ER | Output | External serial register CS 571 | PE28 | LEDIO1 | Output | (V1) LED 572 | | BKBR1 | Input | (V2) Keyboard input scan 573 | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) 574 | | BKBR2 | Input | (V2) Keyboard input scan 575 | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) 576 | | BKBR3 | Input | (V2) Keyboard input scan 577 | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY 578 | | BKBR4 | Input | (V2) Keyboard input scan 579 +------+----------------+--------+--------------------------------------------------- 580 581 ---------------------------------------------------------------------------------------------- 582 583 Serial register input: 584 585 +------+----------------+------------------------------------------------------------ 586 | # | Name | Comment 587 +------+----------------+------------------------------------------------------------ 588 | 4 | HOOK | Hook switch 589 | 5 | BT_LINK | Bluetooth link status 590 | 6 | HOST_WAKE | Bluetooth host wake up 591 | 7 | OK_ETH | Cisco inline power OK status 592 +------+----------------+------------------------------------------------------------ 593 594 ---------------------------------------------------------------------------------------------- 595 596 Chip selects: 597 598 +------+----------------+------------------------------------------------------------ 599 | # | Name | Comment 600 +------+----------------+------------------------------------------------------------ 601 | CS0 | CS0 | Boot flash 602 | CS1 | CS_FLASH | NAND flash 603 | CS2 | CS_DSP | DSP 604 | CS3 | DCS_DRAM | DRAM 605 | CS4 | CS_FLASH2 | (V2) 2nd flash 606 +------+----------------+------------------------------------------------------------ 607 608 ---------------------------------------------------------------------------------------------- 609 610 Interrupts: 611 612 +------+----------------+------------------------------------------------------------ 613 | # | Name | Comment 614 +------+----------------+------------------------------------------------------------ 615 | IRQ1 | IRQ_DSP | DSP interrupt 616 | IRQ3 | S_INTER | DUSLIC ??? 617 | IRQ4 | F_RY_BY | NAND 618 | IRQ7 | IRQ_MAX | MAX 3100 interrupt 619 +------+----------------+------------------------------------------------------------ 620 621 ---------------------------------------------------------------------------------------------- 622 623 Interrupts on PCMCIA pins: 624 625 +------+----------------+------------------------------------------------------------ 626 | # | Name | Comment 627 +------+----------------+------------------------------------------------------------ 628 | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface 629 | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface 630 | IP_A2| RMII1_MDINT | PHY interrupt for #1 631 | IP_A3| RMII2_MDINT | PHY interrupt for #2 632 | IP_A5| HOST_WAKE | (V2) Bluetooth host wake 633 | IP_A6| OK_ETH | (V2) Cisco inline power OK 634 +------+----------------+------------------------------------------------------------ 635 636**************************************************************************************************/ 637 638#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 639#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 640#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 641 642/*************************************************************************************************/ 643 644/* use board specific hardware */ 645#undef CONFIG_WATCHDOG /* watchdog disabled */ 646#define CONFIG_HW_WATCHDOG 647 648/*************************************************************************************************/ 649 650#define CONFIG_CDP_DEVICE_ID 20 651#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta2 */ 652#define CONFIG_CDP_PORT_ID "eth%d" 653#define CONFIG_CDP_CAPABILITIES 0x00000010 654#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME 655#define CONFIG_CDP_PLATFORM "Intracom NetTA2" 656#define CONFIG_CDP_TRIGGER 0x20020001 657#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ 658#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone ? */ 659 660/*************************************************************************************************/ 661 662#define CONFIG_AUTO_COMPLETE 1 663 664/*************************************************************************************************/ 665 666#define CONFIG_CRC32_VERIFY 1 667 668/*************************************************************************************************/ 669 670#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 671 672/*************************************************************************************************/ 673#endif /* __CONFIG_H */ 674