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30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33#ifdef CONFIG_36BIT
34#define CONFIG_PHYS_64BIT
35#endif
36
37#ifdef CONFIG_P1011RDB
38#define CONFIG_P1011
39#endif
40#ifdef CONFIG_P1020RDB
41#define CONFIG_P1020
42#endif
43#ifdef CONFIG_P2010RDB
44#define CONFIG_P2010
45#endif
46#ifdef CONFIG_P2020RDB
47#define CONFIG_P2020
48#endif
49
50#ifdef CONFIG_NAND
51#define CONFIG_NAND_U_BOOT 1
52#define CONFIG_RAMBOOT_NAND 1
53#ifdef CONFIG_NAND_SPL
54#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
55#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
56#else
57#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
58#define CONFIG_SYS_TEXT_BASE 0xf8f82000
59#endif
60#endif
61
62#ifdef CONFIG_SDCARD
63#define CONFIG_RAMBOOT_SDCARD 1
64#define CONFIG_SYS_TEXT_BASE 0x11000000
65#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
66#endif
67
68#ifdef CONFIG_SPIFLASH
69#define CONFIG_RAMBOOT_SPIFLASH 1
70#define CONFIG_SYS_TEXT_BASE 0x11000000
71#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
72#endif
73
74#ifndef CONFIG_SYS_TEXT_BASE
75#define CONFIG_SYS_TEXT_BASE 0xeff80000
76#endif
77
78#ifndef CONFIG_RESET_VECTOR_ADDRESS
79#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
80#endif
81
82#ifndef CONFIG_SYS_MONITOR_BASE
83#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
84#endif
85
86
87#define CONFIG_BOOKE 1
88#define CONFIG_E500 1
89#define CONFIG_MPC85xx 1
90#define CONFIG_FSL_ELBC 1
91
92#define CONFIG_PCI 1
93#if defined(CONFIG_PCI)
94#define CONFIG_PCIE1 1
95#define CONFIG_PCIE2 1
96#define CONFIG_FSL_PCI_INIT 1
97#define CONFIG_FSL_PCIE_RESET 1
98#define CONFIG_SYS_PCI_64BIT 1
99#endif
100#define CONFIG_FSL_LAW 1
101#define CONFIG_TSEC_ENET
102#define CONFIG_ENV_OVERWRITE
103
104#if defined(CONFIG_PCI)
105#define CONFIG_E1000 1
106#endif
107
108#ifndef __ASSEMBLY__
109extern unsigned long get_board_sys_clk(unsigned long dummy);
110#endif
111#define CONFIG_DDR_CLK_FREQ 66666666
112#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
113
114#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
115#define CONFIG_MP
116#endif
117
118#define CONFIG_HWCONFIG
119
120
121
122
123#define CONFIG_L2_CACHE
124#define CONFIG_BTB
125
126#define CONFIG_ADDR_STREAMING
127
128#define CONFIG_ENABLE_36BIT_PHYS 1
129
130#ifdef CONFIG_PHYS_64BIT
131#define CONFIG_ADDR_MAP 1
132#define CONFIG_SYS_NUM_ADDR_MAP 16
133#endif
134
135#define CONFIG_SYS_MEMTEST_START 0x00000000
136#define CONFIG_SYS_MEMTEST_END 0x1fffffff
137#define CONFIG_PANIC_HANG
138
139
140
141
142#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
143#ifdef CONFIG_PHYS_64BIT
144#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
145#else
146#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
147#endif
148#define CONFIG_SYS_L2_SIZE (512 << 10)
149#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
150
151#define CONFIG_SYS_CCSRBAR 0xffe00000
152#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
153
154#if defined(CONFIG_NAND_SPL)
155#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
156#endif
157
158
159#define CONFIG_FSL_DDR2
160#undef CONFIG_FSL_DDR_INTERACTIVE
161#undef CONFIG_SPD_EEPROM
162
163#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
164
165#define CONFIG_SYS_SDRAM_SIZE 1024
166#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
167#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
168
169#define CONFIG_NUM_DDR_CONTROLLERS 1
170#define CONFIG_DIMM_SLOTS_PER_CTLR 1
171#define CONFIG_CHIP_SELECTS_PER_CTRL 1
172
173#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
174#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
175#define CONFIG_SYS_DDR_SBE 0x00FF0000
176
177
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195
196
197
198#define CONFIG_SYS_FLASH_BASE 0xef000000
199
200#ifdef CONFIG_PHYS_64BIT
201#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull
202#else
203#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204#endif
205
206#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
207 BR_PS_16 | BR_V)
208#define CONFIG_FLASH_OR_PRELIM 0xff000ff7
209
210#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
211#define CONFIG_SYS_FLASH_QUIET_TEST
212#define CONFIG_FLASH_SHOW_PROGRESS 45
213
214#define CONFIG_SYS_MAX_FLASH_BANKS 1
215#define CONFIG_SYS_MAX_FLASH_SECT 128
216#undef CONFIG_SYS_FLASH_CHECKSUM
217#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
218#define CONFIG_SYS_FLASH_WRITE_TOUT 500
219
220#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
221 defined(CONFIG_RAMBOOT_SPIFLASH)
222#define CONFIG_SYS_RAMBOOT
223#define CONFIG_SYS_EXTRA_ENV_RELOC
224#else
225#undef CONFIG_SYS_RAMBOOT
226#endif
227
228#define CONFIG_FLASH_CFI_DRIVER
229#define CONFIG_SYS_FLASH_CFI
230#define CONFIG_SYS_FLASH_EMPTY_INFO
231#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
232
233#define CONFIG_BOARD_EARLY_INIT_R
234#define CONFIG_MISC_INIT_R
235#define CONFIG_HWCONFIG
236
237#define CONFIG_SYS_INIT_RAM_LOCK 1
238#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
239#ifdef CONFIG_PHYS_64BIT
240#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
241#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
242
243#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
244 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
245 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
246#else
247#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
248#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
249#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
250#endif
251#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
252
253#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
254 - GENERATED_GBL_DATA_SIZE)
255#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
256
257#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
258#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
259
260#ifndef CONFIG_NAND_SPL
261#define CONFIG_SYS_NAND_BASE 0xffa00000
262#ifdef CONFIG_PHYS_64BIT
263#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
264#else
265#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
266#endif
267#else
268#define CONFIG_SYS_NAND_BASE 0xfff00000
269#ifdef CONFIG_PHYS_64BIT
270#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
271#else
272#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
273#endif
274#endif
275
276#define CONFIG_CMD_NAND
277#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
278#define CONFIG_SYS_MAX_NAND_DEVICE 1
279#define CONFIG_MTD_NAND_VERIFY_WRITE
280#define CONFIG_NAND_FSL_ELBC 1
281#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
282
283
284#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
285#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
286#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
287#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
288#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
289#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
290#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
291
292
293#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
294 | (2<<BR_DECC_SHIFT) \
295 | BR_PS_8 \
296 | BR_MS_FCM \
297 | BR_V)
298
299#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 \
300 | OR_FCM_CSCT \
301 | OR_FCM_CST \
302 | OR_FCM_CHT \
303 | OR_FCM_SCY_1 \
304 | OR_FCM_TRLX \
305 | OR_FCM_EHTR)
306
307#ifdef CONFIG_RAMBOOT_NAND
308#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
309#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
310#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM
311#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
312#else
313#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
314#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
315#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
316#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
317#endif
318
319#define CONFIG_SYS_VSC7385_BASE 0xffb00000
320
321#ifdef CONFIG_PHYS_64BIT
322#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
323#else
324#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
325#endif
326
327#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
328 | BR_PS_8 | BR_V)
329#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
330 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
331 OR_GPCM_EHTR | OR_GPCM_EAD)
332
333
334
335
336
337#define CONFIG_CONS_INDEX 1
338#define CONFIG_SYS_NS16550
339#define CONFIG_SYS_NS16550_SERIAL
340#define CONFIG_SYS_NS16550_REG_SIZE 1
341#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
342#ifdef CONFIG_NAND_SPL
343#define CONFIG_NS16550_MIN_FUNCTIONS
344#endif
345
346#define CONFIG_SYS_CONSOLE_IS_IN_ENV
347
348#define CONFIG_SYS_BAUDRATE_TABLE \
349 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
350
351#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
352#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
353
354
355#define CONFIG_SYS_HUSH_PARSER
356
357
358
359
360#define CONFIG_OF_LIBFDT 1
361#define CONFIG_OF_BOARD_SETUP 1
362#define CONFIG_OF_STDOUT_VIA_ALIAS 1
363
364
365#define CONFIG_FIT 1
366#define CONFIG_FIT_VERBOSE 1
367
368
369#define CONFIG_FSL_I2C
370#define CONFIG_HARD_I2C
371#undef CONFIG_SOFT_I2C
372#define CONFIG_I2C_MULTI_BUS
373#define CONFIG_I2C_CMD_TREE
374#define CONFIG_SYS_I2C_SPEED 400000
375#define CONFIG_SYS_I2C_SLAVE 0x7F
376#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}
377#define CONFIG_SYS_I2C_OFFSET 0x3000
378#define CONFIG_SYS_I2C2_OFFSET 0x3100
379
380
381
382
383#define CONFIG_ID_EEPROM
384#ifdef CONFIG_ID_EEPROM
385#define CONFIG_SYS_I2C_EEPROM_NXID
386#endif
387#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
388#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
389#define CONFIG_SYS_EEPROM_BUS_NUM 1
390
391#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
392
393#define CONFIG_RTC_DS1337
394#define CONFIG_SYS_RTC_DS1337_NOOSC
395#define CONFIG_SYS_I2C_RTC_ADDR 0x68
396
397
398#define CONFIG_FSL_ESPI
399#define CONFIG_SPI_FLASH
400#define CONFIG_SPI_FLASH_SPANSION
401#define CONFIG_CMD_SF
402#define CONFIG_SF_DEFAULT_SPEED 10000000
403#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
404
405
406
407
408
409
410#if defined(CONFIG_PCI)
411
412#define CONFIG_SYS_PCIE2_NAME "Slot 1"
413#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
414#ifdef CONFIG_PHYS_64BIT
415#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
416#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
417#else
418#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
419#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
420#endif
421#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
422#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
423#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
424#ifdef CONFIG_PHYS_64BIT
425#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
426#else
427#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
428#endif
429#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
430
431
432#define CONFIG_SYS_PCIE1_NAME "Slot 2"
433#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
434#ifdef CONFIG_PHYS_64BIT
435#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
436#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
437#else
438#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
439#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
440#endif
441#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
442#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
443#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
444#ifdef CONFIG_PHYS_64BIT
445#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
446#else
447#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
448#endif
449#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
450
451#define CONFIG_PCI_PNP
452
453#undef CONFIG_EEPRO100
454#undef CONFIG_TULIP
455#undef CONFIG_RTL8139
456
457#ifdef CONFIG_RTL8139
458
459#define KSEG1ADDR(x) (x)
460#define _IO_BASE 0x00000000
461#endif
462
463
464#define CONFIG_PCI_SCAN_SHOW
465#define CONFIG_DOS_PARTITION
466
467#endif
468
469
470#if defined(CONFIG_TSEC_ENET)
471#define CONFIG_MII 1
472#define CONFIG_MII_DEFAULT_TSEC 1
473#define CONFIG_TSEC1 1
474#define CONFIG_TSEC1_NAME "eTSEC1"
475#define CONFIG_TSEC2 1
476#define CONFIG_TSEC2_NAME "eTSEC2"
477#define CONFIG_TSEC3 1
478#define CONFIG_TSEC3_NAME "eTSEC3"
479
480#define TSEC1_PHY_ADDR 2
481#define TSEC2_PHY_ADDR 0
482#define TSEC3_PHY_ADDR 1
483
484#define CONFIG_VSC7385_ENET
485
486#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
487#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
488#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
489
490#define TSEC1_PHYIDX 0
491#define TSEC2_PHYIDX 0
492#define TSEC3_PHYIDX 0
493
494
495
496#ifdef CONFIG_VSC7385_ENET
497
498#define CONFIG_VSC7385_IMAGE_SIZE 8192
499#endif
500
501#define CONFIG_ETHPRIME "eTSEC1"
502
503#define CONFIG_PHY_GIGE 1
504
505#endif
506
507
508
509
510#if defined(CONFIG_SYS_RAMBOOT)
511#if defined(CONFIG_RAMBOOT_NAND)
512 #define CONFIG_ENV_IS_IN_NAND 1
513 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
514 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
515#elif defined(CONFIG_RAMBOOT_SDCARD)
516#define CONFIG_ENV_IS_IN_MMC
517#define CONFIG_FSL_FIXED_MMC_LOCATION
518#define CONFIG_ENV_SIZE 0x2000
519#define CONFIG_SYS_MMC_ENV_DEV 0
520#elif defined(CONFIG_RAMBOOT_SPIFLASH)
521 #define CONFIG_ENV_IS_IN_SPI_FLASH
522 #define CONFIG_ENV_SPI_BUS 0
523 #define CONFIG_ENV_SPI_CS 0
524 #define CONFIG_ENV_SPI_MAX_HZ 10000000
525 #define CONFIG_ENV_SPI_MODE 0
526 #define CONFIG_ENV_OFFSET 0x100000
527 #define CONFIG_ENV_SECT_SIZE 0x10000
528 #define CONFIG_ENV_SIZE 0x2000
529#endif
530#else
531 #define CONFIG_ENV_IS_IN_FLASH 1
532 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
533 #define CONFIG_ENV_ADDR 0xfff80000
534 #else
535 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
536 #endif
537 #define CONFIG_ENV_SIZE 0x2000
538 #define CONFIG_ENV_SECT_SIZE 0x20000
539#endif
540
541#define CONFIG_LOADS_ECHO 1
542#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
543
544
545
546
547#include <config_cmd_default.h>
548
549#define CONFIG_CMD_DATE
550#define CONFIG_CMD_ELF
551#define CONFIG_CMD_I2C
552#define CONFIG_CMD_IRQ
553#define CONFIG_CMD_MII
554#define CONFIG_CMD_PING
555#define CONFIG_CMD_SETEXPR
556#define CONFIG_CMD_REGINFO
557
558#if defined(CONFIG_PCI)
559#define CONFIG_CMD_NET
560#define CONFIG_CMD_PCI
561#endif
562
563#undef CONFIG_WATCHDOG
564
565#define CONFIG_MMC 1
566
567#ifdef CONFIG_MMC
568#define CONFIG_BOARD_EARLY_INIT_F 1
569#define CONFIG_CMD_MMC
570#define CONFIG_DOS_PARTITION
571#define CONFIG_FSL_ESDHC
572#define CONFIG_GENERIC_MMC
573#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
574#ifdef CONFIG_P2020
575#define CONFIG_SYS_FSL_ESDHC_USE_PIO
576#endif
577#endif
578
579#define CONFIG_HAS_FSL_DR_USB
580
581#if defined(CONFIG_HAS_FSL_DR_USB)
582#define CONFIG_USB_EHCI
583
584#ifdef CONFIG_USB_EHCI
585#define CONFIG_CMD_USB
586#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
587#define CONFIG_USB_EHCI_FSL
588#define CONFIG_USB_STORAGE
589#endif
590#endif
591
592#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
593#define CONFIG_CMD_EXT2
594#define CONFIG_CMD_FAT
595#define CONFIG_DOS_PARTITION
596#endif
597
598
599
600
601#define CONFIG_SYS_LONGHELP
602#define CONFIG_CMDLINE_EDITING
603#define CONFIG_AUTO_COMPLETE
604#define CONFIG_SYS_LOAD_ADDR 0x2000000
605#define CONFIG_SYS_PROMPT "=> "
606#if defined(CONFIG_CMD_KGDB)
607#define CONFIG_SYS_CBSIZE 1024
608#else
609#define CONFIG_SYS_CBSIZE 256
610#endif
611#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
612
613#define CONFIG_SYS_MAXARGS 16
614#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
615#define CONFIG_SYS_HZ 1000
616
617
618
619
620
621
622#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
623#define CONFIG_SYS_BOOTM_LEN (64 << 20)
624
625#if defined(CONFIG_CMD_KGDB)
626#define CONFIG_KGDB_BAUDRATE 230400
627#define CONFIG_KGDB_SER_INDEX 2
628#endif
629
630
631
632
633
634#if defined(CONFIG_TSEC_ENET)
635#define CONFIG_HAS_ETH0
636#define CONFIG_HAS_ETH1
637#define CONFIG_HAS_ETH2
638#endif
639
640#define CONFIG_HOSTNAME P2020RDB
641#define CONFIG_ROOTPATH "/opt/nfsroot"
642#define CONFIG_BOOTFILE "uImage"
643#define CONFIG_UBOOTPATH u-boot.bin
644
645
646#define CONFIG_LOADADDR 1000000
647
648#define CONFIG_BOOTDELAY 10
649#undef CONFIG_BOOTARGS
650
651#define CONFIG_BAUDRATE 115200
652
653#define CONFIG_EXTRA_ENV_SETTINGS \
654 "netdev=eth0\0" \
655 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
656 "loadaddr=1000000\0" \
657 "tftpflash=tftpboot $loadaddr $uboot; " \
658 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
659 " +$filesize; " \
660 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
661 " +$filesize; " \
662 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
663 " $filesize; " \
664 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
665 " +$filesize; " \
666 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
667 " $filesize\0" \
668 "consoledev=ttyS0\0" \
669 "ramdiskaddr=2000000\0" \
670 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
671 "fdtaddr=c00000\0" \
672 "fdtfile=p2020rdb.dtb\0" \
673 "bdev=sda1\0" \
674 "jffs2nor=mtdblock3\0" \
675 "norbootaddr=ef080000\0" \
676 "norfdtaddr=ef040000\0" \
677 "jffs2nand=mtdblock9\0" \
678 "nandbootaddr=100000\0" \
679 "nandfdtaddr=80000\0" \
680 "nandimgsize=400000\0" \
681 "nandfdtsize=80000\0" \
682 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
683 "vscfw_addr=ef000000\0" \
684 "othbootargs=ramdisk_size=600000\0" \
685 "usbfatboot=setenv bootargs root=/dev/ram rw " \
686 "console=$consoledev,$baudrate $othbootargs; " \
687 "usb start;" \
688 "fatload usb 0:2 $loadaddr $bootfile;" \
689 "fatload usb 0:2 $fdtaddr $fdtfile;" \
690 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
691 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
692 "usbext2boot=setenv bootargs root=/dev/ram rw " \
693 "console=$consoledev,$baudrate $othbootargs; " \
694 "usb start;" \
695 "ext2load usb 0:4 $loadaddr $bootfile;" \
696 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
697 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
698 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
699 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
700 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
701 "bootm $norbootaddr - $norfdtaddr\0" \
702 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
703 "console=$consoledev,$baudrate $othbootargs;" \
704 "nand read 2000000 $nandbootaddr $nandimgsize;" \
705 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
706 "bootm 2000000 - 3000000;\0"
707
708#define CONFIG_NFSBOOTCOMMAND \
709 "setenv bootargs root=/dev/nfs rw " \
710 "nfsroot=$serverip:$rootpath " \
711 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
712 "console=$consoledev,$baudrate $othbootargs;" \
713 "tftp $loadaddr $bootfile;" \
714 "tftp $fdtaddr $fdtfile;" \
715 "bootm $loadaddr - $fdtaddr"
716
717#define CONFIG_HDBOOT \
718 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
719 "console=$consoledev,$baudrate $othbootargs;" \
720 "usb start;" \
721 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
722 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
723 "bootm $loadaddr - $fdtaddr"
724
725#define CONFIG_RAMBOOTCOMMAND \
726 "setenv bootargs root=/dev/ram rw " \
727 "console=$consoledev,$baudrate $othbootargs; " \
728 "tftp $ramdiskaddr $ramdiskfile;" \
729 "tftp $loadaddr $bootfile;" \
730 "tftp $fdtaddr $fdtfile;" \
731 "bootm $loadaddr $ramdiskaddr $fdtaddr"
732
733#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
734
735#endif
736