1/* 2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 3 * Scott McNutt <smcnutt@psyent.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27/*------------------------------------------------------------------------ 28 * BOARD/CPU 29 *----------------------------------------------------------------------*/ 30#define CONFIG_PCI5441 1 /* PCI-5441 board */ 31#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ 32 33#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ 34#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ 35#define CONFIG_SYS_NIOS_SYSID_BASE 0x00920828 /* System id address */ 36#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ 37 38/*------------------------------------------------------------------------ 39 * CACHE -- the following will support II/s and II/f. The II/s does not 40 * have dcache, so the cache instructions will behave as NOPs. 41 *----------------------------------------------------------------------*/ 42#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ 43#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ 44#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ 45#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ 46 47/*------------------------------------------------------------------------ 48 * MEMORY BASE ADDRESSES 49 *----------------------------------------------------------------------*/ 50#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ 51#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ 52#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ 53#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ 54 55/*------------------------------------------------------------------------ 56 * MEMORY ORGANIZATION 57 * -Monitor at top. 58 * -The heap is placed below the monitor. 59 * -Global data is placed below the heap. 60 * -The stack is placed below global data (&grows down). 61 *----------------------------------------------------------------------*/ 62#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128k */ 63#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 64 65#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 66#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) 67#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE) 68#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET 69 70/*------------------------------------------------------------------------ 71 * FLASH (AM29LV065D) 72 *----------------------------------------------------------------------*/ 73#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ 74#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ 75#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ 76#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ 77#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ 78 79/*------------------------------------------------------------------------ 80 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above 81 * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the 82 * reset address, no? This will keep the environment in user region 83 * of flash. NOTE: the monitor length must be multiple of sector size 84 * (which is common practice). 85 *----------------------------------------------------------------------*/ 86#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ 87#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ 88#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ 89#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN) 90 91/*------------------------------------------------------------------------ 92 * CONSOLE 93 *----------------------------------------------------------------------*/ 94#define CONFIG_ALTERA_UART 1 /* Use altera uart */ 95#if defined(CONFIG_ALTERA_JTAG_UART) 96#define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ 97#else 98#define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */ 99#endif 100 101#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ 102#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ 103#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ 104 105#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ 106 107/*------------------------------------------------------------------------ 108 * DEBUG 109 *----------------------------------------------------------------------*/ 110#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ 111 112/*------------------------------------------------------------------------ 113 * TIMEBASE -- 114 * 115 * The high res timer defaults to 1 msec. Since it includes the period 116 * registers, the interrupt frequency can be reduced using TMRCNT. 117 * If the default period is acceptable, TMRCNT can be left undefined. 118 * TMRMS represents the desired mecs per tick (msecs per interrupt). 119 *----------------------------------------------------------------------*/ 120#define CONFIG_SYS_HZ 1000 /* Always 1000 */ 121#define CONFIG_SYS_LOW_RES_TIMER 122#define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ 123#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ 124#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ 125#define CONFIG_SYS_NIOS_TMRCNT \ 126 (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) 127 128 129/* 130 * BOOTP options 131 */ 132#define CONFIG_BOOTP_BOOTFILESIZE 133#define CONFIG_BOOTP_BOOTPATH 134#define CONFIG_BOOTP_GATEWAY 135#define CONFIG_BOOTP_HOSTNAME 136 137 138/* 139 * Command line configuration. 140 */ 141#define CONFIG_CMD_BDI 142#define CONFIG_CMD_ECHO 143#define CONFIG_CMD_SAVEENV 144#define CONFIG_CMD_FLASH 145#define CONFIG_CMD_IMI 146#define CONFIG_CMD_IRQ 147#define CONFIG_CMD_LOADS 148#define CONFIG_CMD_LOADB 149#define CONFIG_CMD_MEMORY 150#define CONFIG_CMD_MISC 151#define CONFIG_CMD_RUN 152#define CONFIG_CMD_SAVES 153 154 155/*------------------------------------------------------------------------ 156 * MISC 157 *----------------------------------------------------------------------*/ 158#define CONFIG_SYS_LONGHELP /* Provide extended help*/ 159#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ 160#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ 161#define CONFIG_SYS_MAXARGS 16 /* Max command args */ 162#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ 163#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ 164#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ 165#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ 166#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 167 168#endif /* __CONFIG_H */ 169