1/* 2 * (C) Copyright 2003-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27/* 28 * High Level Configuration Options 29 * (easy to change) 30 */ 31 32#define CONFIG_MPC5200 33#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ 34#define CONFIG_PM520 1 /* ... on PM520 board */ 35 36#define CONFIG_SYS_TEXT_BASE 0xfff00000 37 38#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ 39 40#define CONFIG_MISC_INIT_R 41 42#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 43 44/* 45 * Serial console configuration 46 */ 47#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 48#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ 49#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 50 51 52/* 53 * PCI Mapping: 54 * 0x40000000 - 0x4fffffff - PCI Memory 55 * 0x50000000 - 0x50ffffff - PCI IO Space 56 */ 57#define CONFIG_PCI 1 58#define CONFIG_PCI_PNP 1 59#define CONFIG_PCI_SCAN_SHOW 1 60#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 61 62#define CONFIG_PCI_MEM_BUS 0x40000000 63#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 64#define CONFIG_PCI_MEM_SIZE 0x10000000 65 66#define CONFIG_PCI_IO_BUS 0x50000000 67#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 68#define CONFIG_PCI_IO_SIZE 0x01000000 69 70#define CONFIG_MII 1 71#define CONFIG_EEPRO100 1 72#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 73#undef CONFIG_NS8382X 74 75 76/* Partitions */ 77#define CONFIG_DOS_PARTITION 78 79/* USB */ 80#if 1 81#define CONFIG_USB_OHCI 82#define CONFIG_USB_STORAGE 83#endif 84 85/* 86 * BOOTP options 87 */ 88#define CONFIG_BOOTP_BOOTFILESIZE 89#define CONFIG_BOOTP_BOOTPATH 90#define CONFIG_BOOTP_GATEWAY 91#define CONFIG_BOOTP_HOSTNAME 92 93 94/* 95 * Command line configuration. 96 */ 97#include <config_cmd_default.h> 98 99#define CONFIG_CMD_BEDBUG 100#define CONFIG_CMD_DATE 101#define CONFIG_CMD_DHCP 102#define CONFIG_CMD_EEPROM 103#define CONFIG_CMD_FAT 104#define CONFIG_CMD_I2C 105#define CONFIG_CMD_IDE 106#define CONFIG_CMD_NFS 107#define CONFIG_CMD_SNTP 108#define CONFIG_CMD_USB 109 110#define CONFIG_CMD_PCI 111 112 113/* 114 * Autobooting 115 */ 116#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 117 118#define CONFIG_PREBOOT "echo;" \ 119 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 120 "echo" 121 122#undef CONFIG_BOOTARGS 123 124#define CONFIG_EXTRA_ENV_SETTINGS \ 125 "netdev=eth0\0" \ 126 "hostname=pm520\0" \ 127 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 128 "nfsroot=${serverip}:${rootpath}\0" \ 129 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 130 "addip=setenv bootargs ${bootargs} " \ 131 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 132 ":${hostname}:${netdev}:off panic=1\0" \ 133 "flash_nfs=run nfsargs addip;" \ 134 "bootm ${kernel_addr}\0" \ 135 "flash_self=run ramargs addip;" \ 136 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 137 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 138 "rootpath=/opt/eldk30/ppc_82xx\0" \ 139 "bootfile=/tftpboot/PM520/uImage\0" \ 140 "" 141 142#define CONFIG_BOOTCOMMAND "run flash_self" 143 144/* 145 * IPB Bus clocking configuration. 146 */ 147#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 148/* 149 * I2C configuration 150 */ 151#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 152#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 153 154#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 155#define CONFIG_SYS_I2C_SLAVE 0x7F 156 157/* 158 * EEPROM configuration 159 */ 160#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 161#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 162#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 163#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 164 165/* 166 * RTC configuration 167 */ 168#define CONFIG_RTC_PCF8563 169#define CONFIG_SYS_I2C_RTC_ADDR 0x51 170 171#define CONFIG_SYS_DOC_BASE 0xE0000000 172#define CONFIG_SYS_DOC_SIZE 0x00100000 173 174#if defined(CONFIG_BOOT_ROM) 175/* 176 * Flash configuration (8,16 or 32 MB) 177 * TEXT base always at 0xFFF00000 178 * ENV_ADDR always at 0xFFF40000 179 * FLASH_BASE at 0xFA000000 for 64 MB 180 * 0xFC000000 for 32 MB 181 * 0xFD000000 for 16 MB 182 * 0xFD800000 for 8 MB 183 */ 184#define CONFIG_SYS_FLASH_BASE 0xFA000000 185#define CONFIG_SYS_FLASH_SIZE 0x04000000 186#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000 187#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 188#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000) 189#else 190/* 191 * Flash configuration (8,16 or 32 MB) 192 * TEXT base always at 0xFFF00000 193 * ENV_ADDR always at 0xFFF40000 194 * FLASH_BASE at 0xFC000000 for 64 MB 195 * 0xFE000000 for 32 MB 196 * 0xFF000000 for 16 MB 197 * 0xFF800000 for 8 MB 198 */ 199#define CONFIG_SYS_FLASH_BASE 0xFC000000 200#define CONFIG_SYS_FLASH_SIZE 0x04000000 201#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000) 202#endif 203#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 204 205#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ 206 207#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 208#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 209#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ 210#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ 211#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 212 213#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ 214 215#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */ 216 217 218/* 219 * Environment settings 220 */ 221#define CONFIG_ENV_IS_IN_FLASH 1 222#define CONFIG_ENV_SIZE 0x10000 223#define CONFIG_ENV_SECT_SIZE 0x40000 224#define CONFIG_ENV_OVERWRITE 1 225 226/* 227 * Memory map 228 */ 229#define CONFIG_SYS_MBAR 0xf0000000 230#define CONFIG_SYS_SDRAM_BASE 0x00000000 231#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 232 233/* Use SRAM until RAM will be available */ 234#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 235#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ 236 237 238#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 239#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 240 241#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 242#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 243# define CONFIG_SYS_RAMBOOT 1 244#endif 245 246#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 247#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 248#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 249 250/* 251 * Ethernet configuration 252 */ 253#define CONFIG_MPC5xxx_FEC 1 254#define CONFIG_MPC5xxx_FEC_MII100 255/* 256 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb 257 */ 258/* #define CONFIG_MPC5xxx_FEC_MII10 */ 259#define CONFIG_PHY_ADDR 0x00 260 261/* 262 * GPIO configuration 263 */ 264#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 265 266/* 267 * Miscellaneous configurable options 268 */ 269#define CONFIG_SYS_LONGHELP /* undef to save memory */ 270#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 271#if defined(CONFIG_CMD_KGDB) 272#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 273#else 274#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 275#endif 276#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 277#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 278#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 279 280#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 281#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 282 283#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 284 285#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 286 287#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 288#if defined(CONFIG_CMD_KGDB) 289# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 290#endif 291 292/* 293 * Various low-level settings 294 */ 295#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 296#define CONFIG_SYS_HID0_FINAL HID0_ICE 297 298#if defined(CONFIG_BOOT_ROM) 299#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE 300#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE 301#define CONFIG_SYS_BOOTCS_CFG 0x00047800 302#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE 303#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE 304#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE 305#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE 306#define CONFIG_SYS_CS1_CFG 0x0004FF00 307#else 308#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 309#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 310#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00 311#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 312#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 313#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE 314#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE 315#define CONFIG_SYS_CS1_CFG 0x00047800 316#endif 317 318#define CONFIG_SYS_CS_BURST 0x00000000 319#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 320 321#define CONFIG_SYS_RESET_ADDRESS 0xff000000 322 323/*----------------------------------------------------------------------- 324 * USB stuff 325 *----------------------------------------------------------------------- 326 */ 327#define CONFIG_USB_CLOCK 0x0001BBBB 328#define CONFIG_USB_CONFIG 0x00005000 329 330/*----------------------------------------------------------------------- 331 * IDE/ATA stuff Supports IDE harddisk 332 *----------------------------------------------------------------------- 333 */ 334 335#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 336 337#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 338#undef CONFIG_IDE_LED /* LED for ide not supported */ 339 340#undef CONFIG_IDE_RESET /* reset for ide supported */ 341#define CONFIG_IDE_PREINIT 342 343#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 344#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */ 345 346#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 347 348#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 349 350/* Offset for data I/O */ 351#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 352 353/* Offset for normal register accesses */ 354#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 355 356/* Offset for alternate registers */ 357#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 358 359/* Interval between registers */ 360#define CONFIG_SYS_ATA_STRIDE 4 361 362#endif /* __CONFIG_H */ 363