1/* 2 * Configuation settings for the esd TASREG board. 3 * 4 * (C) Copyright 2004 5 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * board/config.h - configuration options, board specific 28 */ 29 30#ifndef _TASREG_H 31#define _TASREG_H 32 33#ifndef __ASSEMBLY__ 34#include <asm/m5249.h> 35#endif 36 37/* 38 * High Level Configuration Options 39 * (easy to change) 40 */ 41#define CONFIG_MCF52x2 /* define processor family */ 42#define CONFIG_M5249 /* define processor type */ 43 44#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 45 46#define CONFIG_MCFTMR 47 48#define CONFIG_MCFUART 49#define CONFIG_SYS_UART_PORT (0) 50#define CONFIG_BAUDRATE 19200 51 52#undef CONFIG_WATCHDOG 53 54#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ 55 56 57/* 58 * BOOTP options 59 */ 60#define CONFIG_BOOTP_BOOTFILESIZE 61#define CONFIG_BOOTP_BOOTPATH 62#define CONFIG_BOOTP_GATEWAY 63#define CONFIG_BOOTP_HOSTNAME 64 65 66/* 67 * Command line configuration. 68 */ 69#include <config_cmd_default.h> 70 71#define CONFIG_CMD_BSP 72#define CONFIG_CMD_EEPROM 73#define CONFIG_CMD_I2C 74 75#undef CONFIG_CMD_NET 76 77 78#define CONFIG_BOOTDELAY 3 79 80#define CONFIG_SYS_PROMPT "=> " 81#define CONFIG_SYS_LONGHELP /* undef to save memory */ 82 83#if defined(CONFIG_CMD_KGDB) 84#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 85#else 86#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 87#endif 88#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 89#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 90#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 91 92#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 93#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 94#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 95#define CONFIG_LOOPW 1 /* enable loopw command */ 96#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 97 98#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ 99 100#define CONFIG_SYS_MEMTEST_START 0x400 101#define CONFIG_SYS_MEMTEST_END 0x380000 102 103#define CONFIG_SYS_HZ 1000 104 105/* 106 * Clock configuration: enable only one of the following options 107 */ 108 109#if 0 /* this setting will run the cpu at 11MHz */ 110#define CONFIG_SYS_PLL_BYPASS 1 /* bypass PLL for test purpose */ 111#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */ 112#define CONFIG_SYS_CLK 11289600 /* PLL bypass */ 113#endif 114 115#if 0 /* this setting will run the cpu at 70MHz */ 116#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 117#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */ 118#define CONFIG_SYS_CLK 72185018 /* The next lower speed */ 119#endif 120 121#if 1 /* this setting will run the cpu at 140MHz */ 122#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 123#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ 124#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ 125#endif 126 127/* 128 * Low Level Configuration Settings 129 * (address mappings, register initial values, etc.) 130 * You should know what you are doing if you make changes here. 131 */ 132 133#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 134#define CONFIG_SYS_MBAR2 0x80000000 135 136/*----------------------------------------------------------------------- 137 * I2C 138 */ 139#define CONFIG_SOFT_I2C 140#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ 141#define CONFIG_SYS_I2C_SLAVE 0x7F 142#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ 143#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ 144/* mask of address bits that overflow into the "EEPROM chip address" */ 145#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 146#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ 147 /* 32 byte page write mode using*/ 148 /* last 5 bits of the address */ 149#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 150 151#if defined (CONFIG_SOFT_I2C) 152#if 0 /* push-pull */ 153#define SDA 0x00800000 154#define SCL 0x00000008 155#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN)) 156#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN)) 157#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT)) 158#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT)) 159#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ)) 160#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ)) 161#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;} 162#define I2C_READ ((IN1&SDA)?1:0) 163#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;} 164#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;} 165#define I2C_DELAY {udelay(5);} 166#define I2C_ACTIVE {DIR1|=SDA;} 167#define I2C_TRISTATE {DIR1&=~SDA;} 168#else /* open-collector */ 169#define SDA 0x00800000 170#define SCL 0x00000008 171#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN)) 172#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN)) 173#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT)) 174#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT)) 175#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ)) 176#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ)) 177#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;} 178#define I2C_READ ((IN1&SDA)?1:0) 179#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;} 180#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;} 181#define I2C_DELAY {udelay(5);} 182#define I2C_ACTIVE {DIR1|=SDA;} 183#define I2C_TRISTATE {DIR1&=~SDA;} 184#endif 185#endif 186 187/*----------------------------------------------------------------------- 188 * Definitions for initial stack pointer and data area (in DPRAM) 189 */ 190#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 191#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 192#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 193#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 194 195#define CONFIG_ENV_IS_IN_FLASH 1 196#define CONFIG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/ 197#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ 198#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ 199 200/*----------------------------------------------------------------------- 201 * Start addresses for the final memory configuration 202 * (Set up by the startup code) 203 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 204 */ 205#define CONFIG_SYS_SDRAM_BASE 0x00000000 206#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 207#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 208 209#if 0 /* test-only */ 210#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ 211#endif 212 213#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 214 215#define CONFIG_SYS_MONITOR_LEN 0x20000 216#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ 217#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 218 219/* 220 * For booting Linux, the board info and command line data 221 * have to be in the first 8 MB of memory, since this is 222 * the maximum mapped by the Linux kernel during initialization ?? 223 */ 224#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 225 226/*----------------------------------------------------------------------- 227 * FLASH organization 228 */ 229#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 230#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 231 232#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 233#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 234 235#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 236#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 237#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 238/* 239 * The following defines are added for buggy IOP480 byte interface. 240 * All other boards should use the standard values (CPCI405 etc.) 241 */ 242#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 243#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 244#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 245 246#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 247 248/*----------------------------------------------------------------------- 249 * Cache Configuration 250 */ 251#define CONFIG_SYS_CACHELINE_SIZE 16 252 253#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 254 CONFIG_SYS_INIT_RAM_SIZE - 8) 255#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 256 CONFIG_SYS_INIT_RAM_SIZE - 4) 257#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 258#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 259 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 260 CF_ACR_EN | CF_ACR_SM_ALL) 261#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 262 CF_CACR_DBWE) 263 264/*----------------------------------------------------------------------- 265 * Memory bank definitions 266 */ 267 268/* CS0 - AMD Flash, address 0xffc00000 */ 269#define CONFIG_SYS_CS0_BASE 0xffc00000 270#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ 271/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ 272#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ 273 274/* CS1 - FPGA, address 0xe0000000 */ 275#define CONFIG_SYS_CS1_BASE 0xe0000000 276#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ 277#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ 278 279/*----------------------------------------------------------------------- 280 * Port configuration 281 */ 282#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 283#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ 284#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 285#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 286#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 287#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 288 289#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 290 291/*----------------------------------------------------------------------- 292 * FPGA stuff 293 */ 294#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ 295#define CONFIG_SYS_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/ 296 297/* FPGA program pin configuration */ 298#define CONFIG_SYS_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */ 299#define CONFIG_SYS_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */ 300#define CONFIG_SYS_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */ 301#define CONFIG_SYS_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */ 302#define CONFIG_SYS_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */ 303 304#endif /* _TASREG_H */ 305