1/* 2 * U-boot - Configuration file for BF538F EZ-Kit Lite board 3 */ 4 5#ifndef __CONFIG_BF538F_EZKIT_H__ 6#define __CONFIG_BF538F_EZKIT_H__ 7 8#include <asm/config-pre.h> 9 10 11/* 12 * Processor Settings 13 */ 14#define CONFIG_BFIN_CPU bf538-0.4 15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS 16 17 18/* 19 * Clock Settings 20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 22 */ 23/* CONFIG_CLKIN_HZ is any value in Hz */ 24#define CONFIG_CLKIN_HZ 25000000 25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 26/* 1 = CLKIN / 2 */ 27#define CONFIG_CLKIN_HALF 0 28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 29/* 1 = bypass PLL */ 30#define CONFIG_PLL_BYPASS 0 31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 32/* Values can range from 0-63 (where 0 means 64) */ 33#define CONFIG_VCO_MULT 21 34/* CCLK_DIV controls the core clock divider */ 35/* Values can be 1, 2, 4, or 8 ONLY */ 36#define CONFIG_CCLK_DIV 1 37/* SCLK_DIV controls the system clock divider */ 38/* Values can range from 1-15 */ 39#define CONFIG_SCLK_DIV 4 40 41 42/* 43 * Memory Settings 44 */ 45#define CONFIG_MEM_ADD_WDTH 10 46#define CONFIG_MEM_SIZE 64 47 48#define CONFIG_EBIU_SDRRC_VAL (0x03F6) 49#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3) 50 51#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | AMBEN_ALL | AMCKEN) 52#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) 53#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) 54 55#define CONFIG_SYS_MONITOR_LEN (256 * 1024) 56#define CONFIG_SYS_MALLOC_LEN (384 * 1024) 57 58 59/* 60 * Network Settings 61 */ 62#define ADI_CMDS_NETWORK 1 63#define CONFIG_SMC91111 1 64#define CONFIG_SMC91111_BASE 0x20310300 65#define CONFIG_HOSTNAME bf538f-ezkit 66/* Uncomment next line to use fixed MAC address */ 67/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ 68 69 70/* 71 * Flash Settings 72 */ 73#define CONFIG_FLASH_CFI_DRIVER 74#define CONFIG_SYS_FLASH_BASE 0x20000000 75#define CONFIG_SYS_FLASH_CFI 76#define CONFIG_SYS_FLASH_PROTECTION 77#define CONFIG_SYS_MAX_FLASH_BANKS 1 78#define CONFIG_SYS_MAX_FLASH_SECT 71 79 80 81/* 82 * SPI Settings 83 */ 84#define CONFIG_BFIN_SPI 85#define CONFIG_ENV_SPI_MAX_HZ 30000000 86#define CONFIG_SF_DEFAULT_SPEED 30000000 87#define CONFIG_SPI_FLASH 88#define CONFIG_SPI_FLASH_ALL 89 90 91/* 92 * Env Storage Settings 93 */ 94#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) 95#define CONFIG_ENV_IS_IN_SPI_FLASH 96#define CONFIG_ENV_OFFSET 0x4000 97#define CONFIG_ENV_SIZE 0x2000 98#define CONFIG_ENV_SECT_SIZE 0x2000 99#else 100#define CONFIG_ENV_IS_IN_FLASH 101#define CONFIG_ENV_OFFSET 0x4000 102#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 103#define CONFIG_ENV_SIZE 0x2000 104#define CONFIG_ENV_SECT_SIZE 0x2000 105#endif 106#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) 107#define ENV_IS_EMBEDDED 108#else 109#define CONFIG_ENV_IS_EMBEDDED_IN_LDR 110#endif 111#ifdef ENV_IS_EMBEDDED 112/* WARNING - the following is hand-optimized to fit within 113 * the sector before the environment sector. If it throws 114 * an error during compilation remove an object here to get 115 * it linked after the configuration sector. 116 */ 117# define LDS_BOARD_TEXT \ 118 arch/blackfin/lib/libblackfin.o (.text*); \ 119 arch/blackfin/cpu/libblackfin.o (.text*); \ 120 . = DEFINED(env_offset) ? env_offset : .; \ 121 common/env_embedded.o (.text*); 122#endif 123 124 125/* 126 * I2C Settings 127 */ 128#define CONFIG_BFIN_TWI_I2C 1 129#define CONFIG_HARD_I2C 1 130 131 132/* 133 * Misc Settings 134 */ 135#define CONFIG_RTC_BFIN 136#define CONFIG_UART_CONSOLE 0 137 138 139/* 140 * Pull in common ADI header for remaining command/environment setup 141 */ 142#include <configs/bfin_adi_common.h> 143 144#endif 145