1/* 2 * (C) Copyright 2000 3 * Murray Jensen <Murray.Jensen@cmst.csiro.au> 4 * 5 * (C) Copyright 2000 6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 * Marius Groeger <mgroeger@sysgo.de> 8 * 9 * Configuation settings for the R&S Protocol Board board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 38#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ 39#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */ 40#define CONFIG_CPM2 1 /* Has a CPM2 */ 41 42#define CONFIG_SYS_TEXT_BASE 0xff000000 43#define CONFIG_SYS_LDSCRIPT "board/rsdproto/u-boot.lds" 44 45#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ 46 47/* 48 * select serial console configuration 49 * 50 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 51 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 52 * for SCC). 53 * 54 * if CONFIG_CONS_NONE is defined, then the serial console routines must 55 * defined elsewhere. 56 */ 57#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ 58#define CONFIG_CONS_ON_SCC /* define if console on SCC */ 59#undef CONFIG_CONS_NONE /* define if console on neither */ 60#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ 61 62/* 63 * select ethernet configuration 64 * 65 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 66 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 67 * for FCC) 68 * 69 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 70 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 71 */ 72#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ 73#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ 74#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ 75#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ 76 77#if (CONFIG_ETHER_INDEX == 2) 78 79/* 80 * - Rx-CLK is CLK13 81 * - Tx-CLK is CLK14 82 * - Select bus for bd/buffers (see 28-13) 83 * - Enable Full Duplex in FSMR 84 */ 85# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 86# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 87# define CONFIG_SYS_CPMFCR_RAMTYPE (0) 88# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) 89 90#endif /* CONFIG_ETHER_INDEX */ 91 92 93/* allow to overwrite serial and ethaddr */ 94#define CONFIG_ENV_OVERWRITE 95 96/* enable I2C */ 97#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 98#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ 99#define CONFIG_SYS_I2C_SLAVE 0x30 100 101 102/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 103#define CONFIG_8260_CLKIN 50000000 /* in Hz */ 104 105#define CONFIG_BAUDRATE 115200 106 107 108/* 109 * BOOTP options 110 */ 111#define CONFIG_BOOTP_BOOTFILESIZE 112#define CONFIG_BOOTP_BOOTPATH 113#define CONFIG_BOOTP_GATEWAY 114#define CONFIG_BOOTP_HOSTNAME 115 116 117/* 118 * Command line configuration. 119 */ 120#include <config_cmd_default.h> 121 122#undef CONFIG_CMD_KGDB 123 124 125/* Define this if you want to boot from 0x00000100. If you don't define 126 * this, you will need to program the bootloader to 0xfff00000, and 127 * get the hardware reset config words at 0xfe000000. The simplest 128 * way to do that is to program the bootloader at both addresses. 129 * It is suggested that you just let U-Boot live at 0x00000000. 130 */ 131#define CONFIG_SYS_RSD_BOOT_LOW 1 132 133#define CONFIG_BOOTDELAY 5 134#define CONFIG_BOOTARGS "devfs=mount root=ramfs" 135#define CONFIG_ETHADDR 08:00:3e:26:0a:5a 136#define CONFIG_NETMASK 255.255.0.0 137 138#if defined(CONFIG_CMD_KGDB) 139#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 140#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 141#endif 142 143/* 144 * Miscellaneous configurable options 145 */ 146#define CONFIG_SYS_LONGHELP /* undef to save memory */ 147#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 148#if defined(CONFIG_CMD_KGDB) 149#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 150#else 151#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 152#endif 153#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 154#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 155#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 156 157#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ 158#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ 159 160#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 161 162#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 163 164/* 165 * Low Level Configuration Settings 166 * (address mappings, register initial values, etc.) 167 * You should know what you are doing if you make changes here. 168 */ 169 170/*----------------------------------------------------------------------- 171 * Physical Memory Map 172 */ 173#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */ 174#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */ 175 176#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */ 177#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */ 178 179#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */ 180#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */ 181 182/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */ 183/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */ 184 185#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */ 186#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */ 187 188/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */ 189/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */ 190 191#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */ 192#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100 193 194#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */ 195#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */ 196 197#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */ 198 199#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */ 200#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ 201 202#define CONFIG_SYS_IMMR PHYS_IMMR 203 204/*----------------------------------------------------------------------- 205 * Reset Address 206 * 207 * In order to reset the CPU, U-Boot jumps to a special address which 208 * causes a machine check exception. The default address for this is 209 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when 210 * testing the monitor in RAM using a JTAG debugger. 211 * 212 * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to 213 * cause a bus error on your hardware. 214 */ 215#define CONFIG_SYS_RESET_ADDRESS 0x20000000 216 217/*----------------------------------------------------------------------- 218 * Hard Reset Configuration Words 219 */ 220 221#if defined(CONFIG_SYS_RSD_BOOT_LOW) 222# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) 223#else 224# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0) 225#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */ 226 227/* get the HRCW ISB field from CONFIG_SYS_IMMR */ 228#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\ 229 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\ 230 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) 231 232#define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \ 233 HRCW_DPPC11 | \ 234 CONFIG_SYS_RSD_HRCW_IMMR |\ 235 HRCW_MMR00 | \ 236 HRCW_APPC10 | \ 237 HRCW_CS10PC00 | \ 238 HRCW_MODCK_H0000 |\ 239 CONFIG_SYS_RSD_HRCW_BOOT_FLAGS) 240 241/* no slaves */ 242#define CONFIG_SYS_HRCW_SLAVE1 0 243#define CONFIG_SYS_HRCW_SLAVE2 0 244#define CONFIG_SYS_HRCW_SLAVE3 0 245#define CONFIG_SYS_HRCW_SLAVE4 0 246#define CONFIG_SYS_HRCW_SLAVE5 0 247#define CONFIG_SYS_HRCW_SLAVE6 0 248#define CONFIG_SYS_HRCW_SLAVE7 0 249 250/*----------------------------------------------------------------------- 251 * Definitions for initial stack pointer and data area (in DPRAM) 252 */ 253#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 254#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ 255#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 256#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 257 258/*----------------------------------------------------------------------- 259 * Start addresses for the final memory configuration 260 * (Set up by the startup code) 261 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 262 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend. 263 */ 264#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X 265#define CONFIG_SYS_FLASH_BASE PHYS_FLASH 266/*#define CONFIG_SYS_MONITOR_BASE 0x200000 */ 267#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 268#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE 269#define CONFIG_SYS_RAMBOOT 270#endif 271#define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */ 272#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 273 274/* 275 * For booting Linux, the board info and command line data 276 * have to be in the first 8 MB of memory, since this is 277 * the maximum mapped by the Linux kernel during initialization. 278 */ 279#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 280 281/*----------------------------------------------------------------------- 282 * FLASH and environment organization 283 */ 284#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 285#define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */ 286 287#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */ 288#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */ 289 290/* turn off NVRAM env feature */ 291#undef CONFIG_NVRAM_ENV 292 293#define CONFIG_ENV_IS_IN_FLASH 1 294#define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */ 295#define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */ 296 297/*----------------------------------------------------------------------- 298 * Cache Configuration 299 */ 300#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 301#if defined(CONFIG_CMD_KGDB) 302#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 303#endif 304 305/*----------------------------------------------------------------------- 306 * HIDx - Hardware Implementation-dependent Registers 2-11 307 *----------------------------------------------------------------------- 308 * HID0 also contains cache control - initially enable both caches and 309 * invalidate contents, then the final state leaves only the instruction 310 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 311 * but Soft reset does not. 312 * 313 * HID1 has only read-only information - nothing to set. 314 */ 315#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) 316#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP) 317#define CONFIG_SYS_HID2 0 318 319/*----------------------------------------------------------------------- 320 * RMR - Reset Mode Register 321 *----------------------------------------------------------------------- 322 */ 323#define CONFIG_SYS_RMR 0 324 325/*----------------------------------------------------------------------- 326 * BCR - Bus Configuration 4-25 327 *----------------------------------------------------------------------- 328 */ 329#define CONFIG_SYS_BCR 0x100c0000 330 331/*----------------------------------------------------------------------- 332 * SIUMCR - SIU Module Configuration 4-31 333 *----------------------------------------------------------------------- 334 */ 335 336#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \ 337 SIUMCR_CS10PC01 | SIUMCR_BCTLC01) 338 339/*----------------------------------------------------------------------- 340 * SYPCR - System Protection Control 11-9 341 * SYPCR can only be written once after reset! 342 *----------------------------------------------------------------------- 343 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 344 */ 345#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \ 346 SYPCR_SWRI | SYPCR_SWP) 347 348/*----------------------------------------------------------------------- 349 * TMCNTSC - Time Counter Status and Control 4-40 350 *----------------------------------------------------------------------- 351 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 352 * and enable Time Counter 353 */ 354#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE) 355 356/*----------------------------------------------------------------------- 357 * PISCR - Periodic Interrupt Status and Control 4-42 358 *----------------------------------------------------------------------- 359 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 360 * Periodic timer 361 */ 362#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 363 364/*----------------------------------------------------------------------- 365 * SCCR - System Clock Control 9-8 366 *----------------------------------------------------------------------- 367 */ 368#define CONFIG_SYS_SCCR 0x00000000 369 370/*----------------------------------------------------------------------- 371 * RCCR - RISC Controller Configuration 13-7 372 *----------------------------------------------------------------------- 373 */ 374#define CONFIG_SYS_RCCR 0 375 376/* 377 * Init Memory Controller: 378 */ 379 380#define CONFIG_SYS_PSDMR 0x494D2452 381#define CONFIG_SYS_LSDMR 0x49492552 382 383/* Flash */ 384#define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V) 385#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \ 386 ORxG_BCTLD | \ 387 ORxG_SCY_5_CLK) 388 389/* DPRAM to the PCI BUS on the protocol board */ 390#define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V) 391#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \ 392 ORxG_ACS_DIV4) 393 394/* 60x Bus SDRAM */ 395#define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V) 396#define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \ 397 ORxS_BPD_4 | \ 398 ORxS_ROWST_PBI1_A2 | \ 399 ORxS_NUMR_13 | \ 400 ORxS_IBID) 401 402/* Virtex-FPGA - Register */ 403#define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V) 404#define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \ 405 ORxG_SCY_1_CLK | \ 406 ORxG_ACS_DIV2 | \ 407 ORxG_CSNT ) 408 409/* local bus SDRAM */ 410#define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V) 411#define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \ 412 ORxS_BPD_4 | \ 413 ORxS_ROWST_PBI1_A4 | \ 414 ORxS_NUMR_13) 415 416/* DPRAM to the Sharc-Bus on the protocol board */ 417#define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V) 418#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \ 419 ORxG_ACS_DIV4) 420 421#endif /* __CONFIG_H */ 422