1/* 2 * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> 3 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 4 * 5 * Configuration settings for the HALE TT-01 board. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#ifndef __CONFIG_H 27#define __CONFIG_H 28 29#include <asm/arch/imx-regs.h> 30 31/* High Level Configuration Options */ 32#define CONFIG_ARM1136 33#define CONFIG_MX31 34 35#define CONFIG_DISPLAY_CPUINFO 36#define CONFIG_DISPLAY_BOARDINFO 37 38#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 39#define CONFIG_SETUP_MEMORY_TAGS 40#define CONFIG_INITRD_TAG 41 42#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */ 43#define CONFIG_SYS_TEXT_BASE 0xA0000000 44 45 46/* 47 * Physical Memory Map: 48 * CS settings are defined by i.MX31: 49 * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000 50 * - CS0 and CS1 are 128MB each, at A0000000 and A8000000 51 * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6.. 52 * 53 * HALE set-up of the bluetechnix board for now is: 54 * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface 55 * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0 56 * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM) 57 * the flash chip is a mirrorbit S29WS256N ! 58 * - the PSRAM is hooked to CS5 (0xB6000000) 59 * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1 60 * - 64Mbit = 8MByte (will go away in the production set-up) 61 * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC: 62 * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks 63 * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface 64 * 65 * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM 66 * is not used right now. We should be able to reduce the SOM to NAND flash 67 * only and boot from there. 68 */ 69#define CONFIG_NR_DRAM_BANKS 1 70#define PHYS_SDRAM_1 CSD0_BASE 71#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 72 73#define CONFIG_BOARD_EARLY_INIT_F 74#define CONFIG_BOARD_LATE_INIT 75 76#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 77#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 78#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 79#define CONFIG_SYS_GBL_DATA_OFFSET \ 80 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 81#define CONFIG_SYS_INIT_SP_ADDR \ 82 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) 83 84/* default load address, 1MB up the road */ 85#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000) 86 87/* Size of malloc() pool, make sure possible frame buffer fits */ 88#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024) 89 90/* memtest works on all but the last 1MB (u-boot) and malloc area */ 91#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 92#define CONFIG_SYS_MEMTEST_END \ 93 (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000)) 94 95/* CFI FLASH driver setup */ 96#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 97#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ 98#define CONFIG_FLASH_SPANSION_S29WS_N 99/* 100 * TODO: Bluetechnix (the supplier of the SOM) did define these values 101 * in their original version of u-boot (1.2 or so). This should be 102 * reviewed. 103 * 104 * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 105 * #define CONFIG_SYS_FLASH_PROTECTION 106 */ 107#define CONFIG_SYS_FLASH_BASE CS0_BASE 108#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 109#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */ 110 111/* 112 * FLASH and environment organization, only the Spansion chip is supported: 113 * - it has 254 * 128kB + 8 * 32kB blocks 114 * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF 115 * and 2 sectors with 128k as environment = 116 * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF 117 * - this could be less, but this is only for developer versions of the board 118 * and no-one is going to use the NOR flash anyway. 119 * 120 * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is 121 * way to large, but it avoids ENV overwrite (when updating u-boot) in case 122 * size breaks the next boundary (as it has with 128k). 123 */ 124#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 125#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 126 127#define CONFIG_ENV_IS_IN_FLASH 128#define CONFIG_ENV_SECT_SIZE (128 * 1024) 129#define CONFIG_ENV_SIZE (128 * 1024) 130 131/* Address and size of Redundant Environment Sector */ 132#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 133#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 134 135#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 136 137/* Hardware drivers */ 138 139/* 140 * on TT-01 UART1 pins are used by Audio, so we use UART2 141 * TT-01 implements a hardware that turns off components depending on 142 * the power level. In PL=1 the RS232 transceiver is usually off, 143 * make sure that the transceiver is enabled during PL=1 for testing! 144 */ 145#define CONFIG_MXC_UART 146#define CONFIG_MXC_UART_BASE UART2_BASE 147 148#define CONFIG_MXC_SPI 149#define CONFIG_MXC_GPIO 150 151/* MC13783 connected to CSPI3 and SS0 */ 152#define CONFIG_POWER 153#define CONFIG_POWER_SPI 154#define CONFIG_POWER_FSL 155 156#define CONFIG_FSL_PMIC_BUS 2 157#define CONFIG_FSL_PMIC_CS 0 158#define CONFIG_FSL_PMIC_CLK 1000000 159#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 160#define CONFIG_FSL_PMIC_BITLEN 32 161 162#define CONFIG_RTC_MC13XXX 163 164/* allow to overwrite serial and ethaddr */ 165#define CONFIG_ENV_OVERWRITE 166/* console is UART2 on TT-01 */ 167#define CONFIG_CONS_INDEX 1 168#define CONFIG_BAUDRATE 115200 169 170/* ethernet setup for the onboard smc9118 */ 171#define CONFIG_MII 172#define CONFIG_SMC911X 173/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */ 174#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000) 175#define CONFIG_SMC911X_16_BIT 176 177/* mmc driver */ 178#define CONFIG_MMC 179#define CONFIG_GENERIC_MMC 180#define CONFIG_MXC_MMC 181#define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR 182 183/* video support */ 184#define CONFIG_VIDEO 185#define CONFIG_VIDEO_MX3 186#define CONFIG_CFB_CONSOLE 187#define CONFIG_VIDEO_LOGO 188/* splash image won't work with NAND boot, use preboot script */ 189#define CONFIG_VIDEO_SW_CURSOR 190#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */ 191#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */ 192 193/* allow stdin, stdout and stderr variables to redirect output */ 194#define CONFIG_SYS_CONSOLE_IS_IN_ENV 195#define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */ 196#define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */ 197#define CONFIG_PREBOOT 198 199/* allow decompressing max. 4MB */ 200#define CONFIG_VIDEO_BMP_GZIP 201/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */ 202#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024) 203 204/* 205 * Command definition 206 */ 207 208#include <config_cmd_default.h> 209 210#define CONFIG_CMD_DATE 211#define CONFIG_CMD_PING 212#define CONFIG_CMD_DHCP 213#define CONFIG_CMD_SAVEENV 214#define CONFIG_CMD_NAND 215/* 216 * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support 217 * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports 218 * a software locking scheme. 219 */ 220#define CONFIG_CMD_BMP 221 222#define CONFIG_BOOTDELAY 3 223 224/* 225 * currently a default setting for booting via script is implemented 226 * set user to login name and serverip to tftp host, define your 227 * boot behaviour in bootscript.loginname 228 * 229 * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c) 230 * 231 * This set-up is for the L5F30947T04 by Epson, which is 232 * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync 233 * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL 234 */ 235#define CONFIG_EXTRA_ENV_SETTINGS \ 236"videomode=epson\0" \ 237"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \ 238 "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \ 239"bootcmd=dhcp bootscript.${user}; source\0" 240 241#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */ 242#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */ 243 244/* Miscellaneous configurable options */ 245#define CONFIG_SYS_HUSH_PARSER 246 247#define CONFIG_SYS_LONGHELP /* undef to save memory */ 248#define CONFIG_SYS_PROMPT "TT01> " 249#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 250/* Print Buffer Size */ 251#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 252 sizeof(CONFIG_SYS_PROMPT)+16) 253/* max number of command args */ 254#define CONFIG_SYS_MAXARGS 16 255/* Boot Argument Buffer Size */ 256#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 257 258#define CONFIG_SYS_HZ 1000 259 260#define CONFIG_CMDLINE_EDITING 261 262/* MMC boot support */ 263#define CONFIG_CMD_MMC 264#define CONFIG_DOS_PARTITION 265#define CONFIG_EFI_PARTITION 266#define CONFIG_CMD_EXT2 267#define CONFIG_CMD_FAT 268 269#define CONFIG_NAND_MXC 270#define CONFIG_SYS_MAX_NAND_DEVICE 1 271 272/* 273 * actually this is nothing someone wants to configure! 274 * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init() 275 * is not used by the driver. 276 */ 277#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 278#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 279#define CONFIG_MXC_NAND_HWECC 280 281/* the current u-boot driver does not use the nand flash setup! */ 282#define CONFIG_SYS_NAND_LARGEPAGE 283/* 284 * it's not 16 bit: 285 * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 286 * the current u-boot mxc_nand.c tries to auto-detect, but this only 287 * reads the boot settings during reset (which might be wrong) 288 */ 289 290#endif /* __CONFIG_H */ 291