LXR uboot/include/mpc824x.h

   1/*
   2 * Copyright Rob Taylor, Flying Pig Systems Ltd. 2000.
   3 * Copyright (C) 2001, James Dougherty, jfd@cs.stanford.edu
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef __MPC824X_H__
  25#define __MPC824X_H__
  26
  27#include <config.h>
  28
  29/* CPU Types */
  30#define CPU_TYPE_601            0x01            /* PPC 601       CPU */
  31#define CPU_TYPE_602            0x02            /* PPC 602       CPU */
  32#define CPU_TYPE_603            0x03            /* PPC 603       CPU */
  33#define CPU_TYPE_603E           0x06            /* PPC 603e      CPU */
  34#define CPU_TYPE_603P           0x07            /* PPC 603p      CPU */
  35#define CPU_TYPE_604            0x04            /* PPC 604       CPU */
  36#define CPU_TYPE_604E           0x09            /* PPC 604e      CPU */
  37#define CPU_TYPE_604R           0x0a            /* PPC 604r      CPU */
  38#define CPU_TYPE_750            0x08            /* PPC 750       CPU */
  39#define CPU_TYPE_8240           0x81            /* PPC 8240      CPU */
  40#define CPU_TYPE_8245           0x8081          /* PPC 8245/8241 CPU */
  41#define _CACHE_ALIGN_SIZE       32              /* cache line size */
  42
  43/* spr976 - DMISS data tlb miss address register
  44 * spr977 - DCMP data tlb miss compare register
  45 * spr978 - HASH1 PTEG1 address register
  46 * spr980 - HASH2 PTEG2 address register
  47 * IMISS  - instruction tlb miss address register
  48 * ICMP   - instruction TLB mis compare register
  49 * RPA    - real page address register
  50 * HID0   - hardware implemntation register
  51 * HID2   - instruction address breakpoint register
  52 */
  53
  54/* Kahlua/MPC8240 defines */
  55#define VEN_DEV_ID              0x00021057      /* Vendor and Dev. ID for MPC106 */
  56#define KAHLUA_ID               0x00031057      /* Vendor & Dev Id for Kahlua's PCI */
  57#define KAHLUA2_ID              0x00061057      /* 8245 is aka Kahlua-2 */
  58#define BMC_BASE                0x80000000      /* Kahlua ID in PCI Memory space */
  59#define CHRP_REG_ADDR           0xfec00000      /* MPC107 Config, Map B */
  60#define CHRP_REG_DATA           0xfee00000      /* MPC107 Config, Map B */
  61#define CHRP_ISA_MEM_PHYS       0xfd000000
  62#define CHRP_ISA_MEM_BUS        0x00000000
  63#define CHRP_ISA_MEM_SIZE       0x01000000
  64#define CHRP_ISA_IO_PHYS        0xfe000000
  65#define CHRP_ISA_IO_BUS         0x00000000
  66#define CHRP_ISA_IO_SIZE        0x00800000
  67#define CHRP_PCI_IO_PHYS        0xfe800000
  68#define CHRP_PCI_IO_BUS         0x00800000
  69#define CHRP_PCI_IO_SIZE        0x00400000
  70#define CHRP_PCI_MEM_PHYS       0x80000000
  71#define CHRP_PCI_MEM_BUS        0x80000000
  72#define CHRP_PCI_MEM_SIZE       0x7d000000
  73#define CHRP_PCI_MEMORY_PHYS    0x00000000
  74#define CHRP_PCI_MEMORY_BUS     0x00000000
  75#define CHRP_PCI_MEMORY_SIZE    0x40000000
  76#define PREP_REG_ADDR           0x80000cf8      /* MPC107 Config, Map A */
  77#define PREP_REG_DATA           0x80000cfc      /* MPC107 Config, Map A */
  78#define PREP_ISA_IO_PHYS        0x80000000
  79#define PREP_ISA_IO_BUS         0x00000000
  80#define PREP_ISA_IO_SIZE        0x00800000
  81#define PREP_PCI_IO_PHYS        0x81000000
  82#define PREP_PCI_IO_BUS         0x01000000
  83#define PREP_PCI_IO_SIZE        0x3e800000
  84#define PREP_PCI_MEM_PHYS       0xc0000000
  85#define PREP_PCI_MEM_BUS        0x00000000
  86#define PREP_PCI_MEM_SIZE       0x3f000000
  87#define PREP_PCI_MEMORY_PHYS    0x00000000
  88#define PREP_PCI_MEMORY_BUS     0x80000000
  89#define PREP_PCI_MEMORY_SIZE    0x80000000
  90#define MPC107_PCI_CMD          0x80000004      /* MPC107 PCI cmd reg */
  91#define MPC107_PCI_STAT         0x80000006      /* MPC107 PCI status reg */
  92#define PROC_INT1_ADR           0x800000a8      /* MPC107 Processor i/f cfg1 */
  93#define PROC_INT2_ADR           0x800000ac      /* MPC107 Processor i/f cfg2 */
  94#define MEM_CONT1_ADR           0x800000f0      /* MPC107 Memory control config. 1 */
  95#define MEM_CONT2_ADR           0x800000f4      /* MPC107 Memory control config. 2 */
  96#define MEM_CONT3_ADR           0x800000f8      /* MPC107 Memory control config. 3 */
  97#define MEM_CONT4_ADR           0x800000fc      /* MPC107 Memory control config. 4 */
  98#define MEM_ERREN1_ADR          0x800000c0      /* MPC107 Memory error enable 1 */
  99#define MEM_START1_ADR          0x80000080      /* MPC107 Memory starting addr */
 100#define MEM_START2_ADR          0x80000084      /* MPC107 Memory starting addr-lo */
 101#define XMEM_START1_ADR         0x80000088      /* MPC107 Extended mem. start addr-hi*/
 102#define XMEM_START2_ADR         0x8000008c      /* MPC107 Extended mem. start addr-lo*/
 103#define MEM_END1_ADR            0x80000090      /* MPC107 Memory ending address */
 104#define MEM_END2_ADR            0x80000094      /* MPC107 Memory ending addr-lo */
 105#define XMEM_END1_ADR           0x80000098      /* MPC107 Extended mem. end addrs-hi */
 106#define XMEM_END2_ADR           0x8000009c      /* MPC107 Extended mem. end addrs-lo*/
 107#define OUT_DRV_CONT            0x80000073      /* MPC107 Output Driver Control reg */
 108#define MEM_EN_ADR              0x800000a0      /* Memory bank enable */
 109#define PAGE_MODE               0x800000a3      /* MPC107 Page Mode Counter/Timer */
 110
 111/*-----------------------------------------------------------------------
 112 * Exception offsets (PowerPC standard)
 113 */
 114#define EXC_OFF_RESERVED0       0x0000  /* Reserved */
 115#define EXC_OFF_SYS_RESET       0x0100  /* System reset */
 116#define EXC_OFF_MACH_CHCK       0x0200  /* Machine Check */
 117#define EXC_OFF_DATA_STOR       0x0300  /* Data Storage */
 118#define EXC_OFF_INS_STOR        0x0400  /* Instruction Storage */
 119#define EXC_OFF_EXTERNAL        0x0500  /* External */
 120#define EXC_OFF_ALIGN           0x0600  /* Alignment */
 121#define EXC_OFF_PROGRAM         0x0700  /* Program */
 122#define EXC_OFF_FPUNAVAIL       0x0800  /* Floating-point Unavailable */
 123#define EXC_OFF_DECR            0x0900  /* Decrementer */
 124#define EXC_OFF_RESERVED1       0x0A00  /* Reserved */
 125#define EXC_OFF_RESERVED2       0x0B00  /* Reserved */
 126#define EXC_OFF_SYS_CALL        0x0C00  /* System Call */
 127#define EXC_OFF_TRACE           0x0D00  /* Trace */
 128#define EXC_OFF_FPUNASSIST      0x0E00  /* Floating-point Assist */
 129
 130        /* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */
 131        /* these found in DINK code  - may not apply to 8240*/
 132#define EXC_OFF_PMI             0x0F00  /* Performance Monitoring Interrupt */
 133#define EXC_OFF_VMXUI           0x0F20  /* VMX (AltiVec) Unavailable Interrupt */
 134
 135        /* 0x1000 - 0x2FFF are implementation specific */
 136        /* these found in DINK code  - may not apply to 8240 */
 137#define EXC_OFF_ITME            0x1000  /* Instruction Translation Miss Exception */
 138#define EXC_OFF_DLTME           0x1100  /* Data Load Translation Miss Exception */
 139#define EXC_OFF_DSTME           0x1200  /* Data Store Translation Miss Exception */
 140#define EXC_OFF_IABE            0x1300  /* Instruction Addr Breakpoint Exception */
 141#define EXC_OFF_SMIE            0x1400  /* System Management Interrupt Exception */
 142#define EXC_OFF_JMDDI           0x1600  /* Java Mode denorm detect Interr -- WTF??*/
 143#define EXC_OFF_RMTE            0x2000  /* Run Mode or Trace Exception */
 144
 145#define _START_OFFSET           EXC_OFF_SYS_RESET
 146
 147#define MAP_A_CONFIG_ADDR_HIGH  0x8000  /* Upper half of CONFIG_ADDR for Map A */
 148#define MAP_A_CONFIG_ADDR_LOW   0x0CF8  /* Lower half of CONFIG_ADDR for Map A */
 149#define MAP_A_CONFIG_DATA_HIGH  0x8000  /* Upper half of CONFIG_DAT for Map A */
 150#define MAP_A_CONFIG_DATA_LOW   0x0CFC  /* Lower half of CONFIG_DAT for Map A */
 151#define MAP_B_CONFIG_ADDR_HIGH  0xfec0  /* Upper half of CONFIG_ADDR for Map B */
 152#define MAP_B_CONFIG_ADDR_LOW   0x0000  /* Lower half of CONFIG_ADDR for Map B */
 153#define MAP_B_CONFIG_DATA_HIGH  0xfee0  /* Upper half of CONFIG_DAT for Map B */
 154#define MAP_B_CONFIG_DATA_LOW   0x0000  /* Lower half of CONFIG_DAT for Map B */
 155
 156
 157#if defined(CONFIG_SYS_ADDR_MAP_A)
 158#define CONFIG_ADDR_HIGH    MAP_A_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
 159#define CONFIG_ADDR_LOW     MAP_A_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
 160#define CONFIG_DATA_HIGH    MAP_A_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
 161#define CONFIG_DATA_LOW     MAP_A_CONFIG_DATA_LOW   /* Lower half of CONFIG_DAT */
 162#else /* Assume Map B, default */
 163#define CONFIG_ADDR_HIGH    MAP_B_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
 164#define CONFIG_ADDR_LOW     MAP_B_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
 165#define CONFIG_DATA_HIGH    MAP_B_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
 166#define CONFIG_DATA_LOW     MAP_B_CONFIG_DATA_LOW   /* Lower half of CONFIG_DAT */
 167#endif
 168
 169#define CONFIG_ADDR     (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW)
 170
 171#define CONFIG_DATA     (CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW)
 172
 173/* Macros to write to config registers. addr should be a constant in all cases */
 174
 175#define CONFIG_WRITE_BYTE( addr, data ) \
 176  __asm__ __volatile__( \
 177  " stwbrx %1, 0, %0\n \
 178    sync\n \
 179    stb %3, %4(%2)\n \
 180    sync " \
 181  : /* no output */ \
 182  : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
 183    "b" (CONFIG_DATA), "r" (data), \
 184    "n" ((addr) & 3));
 185
 186#define CONFIG_WRITE_HALFWORD( addr, data ) \
 187  __asm__ __volatile__( \
 188  " stwbrx %1, 0, %0\n \
 189    sync\n \
 190    sthbrx %3, %4, %2\n \
 191    sync " \
 192  : /* no output */ \
 193  : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
 194    "r" (CONFIG_DATA), "r" (data), \
 195    "b" ((addr) & 3));
 196
 197/* this assumes it's writeing on word boundaries*/
 198#define CONFIG_WRITE_WORD( addr, data ) \
 199  __asm__ __volatile__( \
 200  " stwbrx %1, 0, %0\n \
 201    sync\n \
 202    stwbrx %3, 0, %2\n \
 203    sync " \
 204  : /* no output */ \
 205  : "r" (CONFIG_ADDR), "r" (addr), \
 206    "r" (CONFIG_DATA), "r" (data));
 207
 208/* Configuration register reads*/
 209
 210#define CONFIG_READ_BYTE( addr, reg ) \
 211  __asm__ ( \
 212  " stwbrx %1, 0, %2\n \
 213    sync\n \
 214    lbz   %0, %4(%3)\n \
 215    sync " \
 216  : "=r" (reg) \
 217  : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
 218    "b" (CONFIG_DATA), "n" ((addr) & 3));
 219
 220
 221#define CONFIG_READ_HALFWORD( addr, reg ) \
 222  __asm__ ( \
 223  " stwbrx %1, 0, %2\n \
 224    sync\n \
 225    lhbrx %0, %4, %3\n \
 226    sync " \
 227  : "=r" (reg) \
 228  : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
 229    "r" (CONFIG_DATA), \
 230    "b" ((addr) & 3));
 231
 232/* this assumes it's reading on word boundaries*/
 233#define CONFIG_READ_WORD( addr, reg ) \
 234  __asm__ ( \
 235  " stwbrx %1, 0, %2\n \
 236    sync\n \
 237    lwbrx %0, 0, %3\n \
 238    sync " \
 239  : "=r" (reg) \
 240  : "r" (addr), "r" (CONFIG_ADDR),\
 241    "r" (CONFIG_DATA));
 242
 243/*
 244 *  configuration register 'addresses'.
 245 *  These are described in chaper 5 of the 8240 users manual.
 246 *  Where the register has an abreviation in the manual, this has
 247 *  been usaed here, otherwise a name in keeping with the norm has
 248 *  been invented.
 249 *  Note that some of these registers aren't documented in the manual.
 250 */
 251
 252#define PCICR           0x80000004  /* PCI Command Register */
 253#define PCISR           0x80000006  /* PCI Status Register */
 254#define REVID           0x80000008  /* CPU revision id */
 255#define PIR             0x80000009  /* PCI Programming Interface Register */
 256#define PBCCR           0x8000000b  /* PCI Base Class Code Register */
 257#define PCLSR           0x8000000c  /* Processor Cache Line Size Register */
 258#define PLTR            0x8000000d  /* PCI Latancy Timer Register */
 259#define PHTR            0x8000000e  /* PCI Header Type Register */
 260#define BISTCTRL        0x8000000f  /* BIST Control */
 261#define LMBAR           0x80000010  /* Local Base Address Register */
 262#define PCSRBAR         0x80000014  /* PCSR Base Address Register */
 263#define ILR             0x8000003c  /* PCI Interrupt Line Register */
 264#define IPR             0x8000003d  /* Interrupt Pin Register */
 265#define MINGNT          0x8000003e  /* MIN GNI */
 266#define MAXLAT          0x8000003f  /* MAX LAT */
 267#define PCIACR          0x80000046  /* PCI Arbiter Control Register */
 268#define PMCR1           0x80000070  /* Power management config. 1 */
 269#define PMCR2           0x80000072  /* Power management config. 2 */
 270#define ODCR            0x80000073  /* Output Driver Control Register */
 271#define CLKDCR          0x80000074  /* CLK Driver Control Register */
 272#if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
 273#define MIOCR1          0x80000076  /* Miscellaneous I/O Control Register 1 */
 274#define MIOCR2          0x80000077  /* Miscellaneous I/O Control Register 2 */
 275#endif
 276#define EUMBBAR         0x80000078  /* Embedded Utilities Memory Block Base Address Register */
 277#define EUMBBAR_VAL     0x80500000  /* PCI Relocation offset for EUMB region */
 278#define EUMBSIZE        0x00100000  /* Size of EUMB region */
 279
 280#define MSAR1           0x80000080  /* Memory Starting Address Register 1 */
 281#define MSAR2           0x80000084  /* Memory Starting Address Register 2 */
 282#define EMSAR1          0x80000088  /* Extended Memory Starting Address Register 1*/
 283#define EMSAR2          0x8000008c  /* Extended Memory Starting Address Register 2*/
 284#define MEAR1           0x80000090  /* Memory Ending Address Register 1 */
 285#define MEAR2           0x80000094  /* Memory Ending Address Register 2 */
 286#define EMEAR1          0x80000098  /* Extended Memory Ending Address Register 1 */
 287#define EMEAR2          0x8000009c  /* Extended Memory Ending Address Register 2 */
 288#define MBER            0x800000a0  /* Memory bank Enable Register*/
 289#define MPMR            0x800000a3  /* Memory Page Mode Register (stores PGMAX) */
 290#define PICR1           0x800000a8  /* Processor Interface Configuration Register 1 */
 291#define PICR2           0x800000ac  /* Processor Interface Configuration Register 2 */
 292#define ECCSBECR        0x800000b8  /* ECC Single-Bit Error Counter Register */
 293#define ECCSBETR        0x800000b8  /* ECC Single-Bit Error Trigger Register */
 294#define ERRENR1         0x800000c0  /* Error Enableing Register 1 */
 295#define ERRENR2         0x800000c4  /* Error Enableing Register 2 */
 296#define ERRDR1          0x800000c1  /* Error Detection Register 1 */
 297#define IPBESR          0x800000c3  /* Internal Processor Error Status Register */
 298#define ERRDR2          0x800000c5  /* Error Detection Register 2 */
 299#define PBESR           0x800000c7  /* PCI Bus Error Status Register */
 300#define PBEAR           0x800000c8  /* Processor/PCI Bus Error Status Register */
 301#define AMBOR           0x800000e0  /* Address Map B Options Register */
 302#define PCMBCR          0x800000e1  /* PCI/Memory Buffer Configuration */
 303#define MCCR1           0x800000f0  /* Memory Control Configuration Register 1 */
 304#define MCCR2           0x800000f4  /* Memory Control Configuration Register 2 */
 305#define MCCR3           0x800000f8  /* Memory Control Configuration Register 3 */
 306#define MCCR4           0x800000fc  /* Memory Control Configuration Register 4 */
 307
 308/* some values for some of the above */
 309
 310#define PICR1_CF_APARK          0x00000008
 311#define PICR1_LE_MODE           0x00000020
 312#define PICR1_ST_GATH_EN        0x00000040
 313#if defined(CONFIG_MPC8240)
 314#define PICR1_EN_PCS            0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
 315#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
 316#define PICR1_NO_BUSW_CK        0x00000080 /* no bus width check for flash writes */
 317#define PICR1_DEC               0x00000100 /* Time Base enable on 8245/8241 */
 318#define ERCR1                   0x800000d0  /* Extended ROM Configuration Register 1 */
 319#define ERCR2                   0x800000d4  /* Extended ROM Configuration Register 2 */
 320#define ERCR3                   0x800000d8  /* Extended ROM Configuration Register 3 */
 321#define ERCR4                   0x800000dc  /* Extended ROM Configuration Register 4 */
 322#define MIOCR1                  0x80000076  /* Miscellaneous I/O Control Register 1 */
 323#define MIOCR1_ADR_X            0x80000074  /* Miscellaneous I/O Control Register 1 */
 324#define MIOCR1_SHIFT            2
 325#define MIOCR2                  0x80000077  /* Miscellaneous I/O Control Register 2 */
 326#define MIOCR2_ADR_X            0x80000074  /* Miscellaneous I/O Control Register 1 */
 327#define MIOCR2_SHIFT            3
 328#define ODCR_ADR_X              0x80000070      /* Output Driver Control register */
 329#define ODCR_SHIFT              3
 330#define PMCR2_ADR               0x80000072      /* Power Mgmnt Cfg 2 register */
 331#define PMCR2_ADR_X             0x80000070
 332#define PMCR2_SHIFT             3
 333#define PMCR1_ADR               0x80000070      /* Power Mgmnt Cfg 1 reister */
 334#else
 335#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 336#endif
 337#define PICR1_CF_DPARK          0x00000200
 338#define PICR1_MCP_EN            0x00000800
 339#define PICR1_FLASH_WR_EN       0x00001000
 340#ifdef CONFIG_MPC8240
 341#define PICR1_ADDRESS_MAP       0x00010000
 342#define PIRC1_MSK               0xff000000
 343#endif
 344#define PICR1_PROC_TYPE_MSK     0x00060000
 345#define PICR1_PROC_TYPE_603E    0x00040000
 346#define PICR1_RCS0              0x00100000
 347
 348#define PICR2_CF_SNOOP_WS_MASK  0x000c0000
 349#define PICR2_CF_SNOOP_WS_0WS   0x00000000
 350#define PICR2_CF_SNOOP_WS_1WS   0x00040000
 351#define PICR2_CF_SNOOP_WS_2WS   0x00080000
 352#define PICR2_CF_SNOOP_WS_3WS   0x000c0000
 353#define PICR2_CF_APHASE_WS_MASK 0x0000000c
 354#define PICR2_CF_APHASE_WS_0WS  0x00000000
 355#define PICR2_CF_APHASE_WS_1WS  0x00000004
 356#define PICR2_CF_APHASE_WS_2WS  0x00000008
 357#define PICR2_CF_APHASE_WS_3WS  0x0000000c
 358
 359#define MCCR1_ROMNAL_SHIFT      28
 360#define MCCR1_ROMNAL_MSK        0xf0000000
 361#define MCCR1_ROMFAL_SHIFT      23
 362#define MCCR1_ROMFAL_MSK        0x0f800000
 363#define MCCR1_DBUS_SIZE0        0x00400000
 364#define MCCR1_BURST             0x00100000
 365#define MCCR1_MEMGO             0x00080000
 366#define MCCR1_SREN              0x00040000
 367#if defined(CONFIG_MPC8240)
 368#define MCCR1_RAM_TYPE          0x00020000
 369#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
 370#define MCCR1_SDRAM_EN          0x00020000
 371#else
 372#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 373#endif
 374#define MCCR1_PCKEN             0x00010000
 375#define MCCR1_BANK1ROW_SHIFT    2
 376#define MCCR1_BANK2ROW_SHIFT    4
 377#define MCCR1_BANK3ROW_SHIFT    6
 378#define MCCR1_BANK4ROW_SHIFT    8
 379#define MCCR1_BANK5ROW_SHIFT    10
 380#define MCCR1_BANK6ROW_SHIFT    12
 381#define MCCR1_BANK7ROW_SHIFT    14
 382
 383#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
 384#define MCCR2_TS_WAIT_TIMER_SHIFT 29
 385#define MCCR2_ASRISE_MSK        0x1e000000
 386#define MCCR2_ASRISE_SHIFT      25
 387#define MCCR2_ASFALL_MSK        0x01e00000
 388#define MCCR2_ASFALL_SHIFT      21
 389
 390#define MCCR2_INLINE_PAR_NOT_ECC    0x00100000
 391#define MCCR2_WRITE_PARITY_CHK  0x00080000
 392#define MCCR2_INLFRD_PARECC_CHK_EN  0x00040000
 393#ifdef CONFIG_MPC8240
 394#define MCCR2_ECC_EN            0x00020000
 395#define MCCR2_EDO               0x00010000
 396#endif
 397#define MCCR2_REFINT_MSK        0x0000fffc
 398#define MCCR2_REFINT_SHIFT      2
 399#define MCCR2_RSV_PG            0x00000002
 400#define MCCR2_PMW_PAR           0x00000001
 401
 402#define MCCR3_BSTOPRE2TO5_MSK   0xf0000000 /*BSTOPRE[2-5]*/
 403#define MCCR3_BSTOPRE2TO5_SHIFT 28
 404#define MCCR3_REFREC_MSK        0x0f000000
 405#define MCCR3_REFREC_SHIFT      24
 406#ifdef CONFIG_MPC8240
 407#define MCCR3_RDLAT_MSK         0x00f00000
 408#define MCCR3_RDLAT_SHIFT       20
 409#define MCCR3_CPX               0x00010000
 410#define MCCR3_RAS6P_MSK         0x00078000
 411#define MCCR3_RAS6P_SHIFT       15
 412#define MCCR3_CAS5_MSK          0x00007000
 413#define MCCR3_CAS5_SHIFT        12
 414#define MCCR3_CP4_MSK           0x00000e00
 415#define MCCR3_CP4_SHIFT         9
 416#define MCCR3_CAS3_MSK          0x000001c0
 417#define MCCR3_CAS3_SHIFT        6
 418#define MCCR3_RCD2_MSK          0x00000038
 419#define MCCR3_RCD2_SHIFT        3
 420#define MCCR3_RP1_MSK           0x00000007
 421#define MCCR3_RP1_SHIFT         0
 422#endif
 423
 424#define MCCR4_PRETOACT_MSK      0xf0000000
 425#define MCCR4_PRETOACT_SHIFT    28
 426#define MCCR4_ACTTOPRE_MSK      0x0f000000
 427#define MCCR4_ACTTOPRE_SHIFT    24
 428#define MCCR4_WMODE             0x00800000
 429#define MCCR4_INLINE            0x00400000
 430#if defined(CONFIG_MPC8240)
 431#define MCCR4_BIT21             0x00200000 /* this include cos DINK code sets it- unknown function*/
 432#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
 433#define MCCR4_EXTROM            0x00200000 /* enables Extended ROM space */
 434#else
 435#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 436#endif
 437#define MCCR4_REGISTERED        0x00100000
 438#define MCCR4_BSTOPRE0TO1_MSK   0x000c0000 /*BSTOPRE[0-1]*/
 439#define MCCR4_BSTOPRE0TO1_SHIFT 18
 440#define MCCR4_REGDIMM           0x00008000
 441#define MCCR4_SDMODE_MSK        0x00007f00
 442#define MCCR4_SDMODE_SHIFT      8
 443#define MCCR4_ACTTORW_MSK       0x000000f0
 444#define MCCR4_ACTTORW_SHIFT     4
 445#define MCCR4_BSTOPRE6TO9_MSK   0x0000000f /*BSTOPRE[6-9]*/
 446#define MCCR4_BSTOPRE6TO9_SHIFT 0
 447#define MCCR4_DBUS_SIZE2_SHIFT  17
 448
 449#define MICR_ADDR_MASK          0x0ff00000
 450#define MICR_ADDR_SHIFT         20
 451#define MICR_EADDR_MASK         0x30000000
 452#define MICR_EADDR_SHIFT        28
 453
 454/*eumb and epic config*/
 455
 456#define EPIC_FPR                0x00041000
 457#define EPIC_GCR                0x00041020
 458#define EPIC_EICR               0x00041030
 459#define EPIC_EVI                0x00041080
 460#define EPIC_PI                 0x00041090
 461#define EPIC_SVR                0x000410E0
 462#define EPIC_TFRR               0x000410F0
 463
 464/*
 465 * Note the information for these is rather mangled in the 8240 manual.
 466 * These are guesses.
 467 */
 468
 469#define EPIC_GTCCR0             0x00041100
 470#define EPIC_GTCCR1             0x00041140
 471#define EPIC_GTCCR2             0x00041180
 472#define EPIC_GTCCR3             0x000411C0
 473#define EPIC_GTBCR0             0x00041110
 474#define EPIC_GTBCR1             0x00041150
 475#define EPIC_GTBCR2             0x00041190
 476#define EPIC_GTBCR3             0x000411D0
 477#define EPIC_GTVPR0             0x00041120
 478#define EPIC_GTVPR1             0x00041160
 479#define EPIC_GTVPR2             0x000411a0
 480#define EPIC_GTVPR3             0x000411e0
 481#define EPIC_GTDR0              0x00041130
 482#define EPIC_GTDR1              0x00041170
 483#define EPIC_GTDR2              0x000411b0
 484#define EPIC_GTDR3              0x000411f0
 485
 486#define EPIC_IVPR0              0x00050200
 487#define EPIC_IVPR1              0x00050220
 488#define EPIC_IVPR2              0x00050240
 489#define EPIC_IVPR3              0x00050260
 490#define EPIC_IVPR4              0x00050280
 491
 492#define EPIC_SVPR0              0x00050200
 493#define EPIC_SVPR1              0x00050220
 494#define EPIC_SVPR2              0x00050240
 495#define EPIC_SVPR3              0x00050260
 496#define EPIC_SVPR4              0x00050280
 497#define EPIC_SVPR5              0x000502A0
 498#define EPIC_SVPR6              0x000502C0
 499#define EPIC_SVPR7              0x000502E0
 500#define EPIC_SVPR8              0x00050300
 501#define EPIC_SVPR9              0x00050320
 502#define EPIC_SVPRa              0x00050340
 503#define EPIC_SVPRb              0x00050360
 504#define EPIC_SVPRc              0x00050380
 505#define EPIC_SVPRd              0x000503A0
 506#define EPIC_SVPRe              0x000503C0
 507#define EPIC_SVPRf              0x000503E0
 508
 509/* MPC8240 Byte Swap/PCI Support Macros */
 510#define BYTE_SWAP_16_BIT(x)    ( (((x) & 0x00ff) << 8) | ( (x) >> 8) )
 511#define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
 512                     (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
 513#define PCISWAP(x)   LONGSWAP(x)
 514
 515#ifndef __ASSEMBLY__
 516
 517/*
 518 * MPC107 Support
 519 *
 520 */
 521unsigned int mpc824x_mpc107_getreg(unsigned int regNum);
 522void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal);
 523void mpc824x_mpc107_write8(unsigned int address, unsigned char data);
 524void mpc824x_mpc107_write16(unsigned int address, unsigned short data);
 525void mpc824x_mpc107_write32(unsigned int address, unsigned int data);
 526unsigned char mpc824x_mpc107_read8(unsigned int address);
 527unsigned short mpc824x_mpc107_read16(unsigned int address);
 528unsigned int mpc824x_mpc107_read32(unsigned int address);
 529unsigned int mpc824x_eummbar_read(unsigned int regNum);
 530void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal);
 531
 532#ifdef CONFIG_PCI
 533struct pci_controller;
 534void pci_cpm824x_init(struct pci_controller* hose);
 535#endif
 536
 537#endif /* __ASSEMBLY__ */
 538
 539#endif /* __MPC824X_H__ */
 540