LXR uboot/nand_spl/board/freescale/p1023rds/nand

   1/*
   2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3 * Author: Roy Zang <tie-fei.zang@freescale.com>
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License as
   7 * published by the Free Software Foundation; either version 2 of
   8 * the License, or (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 *
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 * MA 02111-1307 USA
  20 *
  21 */
  22
  23#include <common.h>
  24#include <ns16550.h>
  25#include <asm/io.h>
  26#include <nand.h>
  27#include <asm/fsl_law.h>
  28#include <asm/fsl_ddr_sdram.h>
  29#include <asm/global_data.h>
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32
  33/* Fixed sdram init -- doesn't use serial presence detect. */
  34void sdram_init(void)
  35{
  36        ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
  37
  38        set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
  39
  40        __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
  41        __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
  42        __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
  43        __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
  44        __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
  45        __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
  46        __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
  47        __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
  48        __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
  49        __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
  50        __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
  51        __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
  52        __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
  53        __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
  54        __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
  55        __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
  56        __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
  57        __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
  58        __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
  59        __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
  60        /* Set, but do not enable the memory */
  61        __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
  62
  63        asm volatile("sync;isync");
  64        udelay(500);
  65
  66        /* Let the controller go */
  67        out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
  68}
  69
  70void board_init_f(ulong bootflag)
  71{
  72        u32 plat_ratio;
  73        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  74
  75        /* initialize selected port with appropriate baud rate */
  76        plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  77        plat_ratio >>= 1;
  78        gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
  79        NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  80                        gd->bus_clk / 16 / CONFIG_BAUDRATE);
  81
  82        puts("\nNAND boot... ");
  83        /* Initialize the DDR3 */
  84        sdram_init();
  85        /* copy code to RAM and jump to it - this should not return */
  86        /* NOTE - code has to be copied out of NAND buffer before
  87         * other blocks can be read.
  88         */
  89        relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
  90                        CONFIG_SYS_NAND_U_BOOT_RELOC);
  91}
  92
  93void board_init_r(gd_t *gd, ulong dest_addr)
  94{
  95        nand_boot();
  96}
  97
  98void putc(char c)
  99{
 100        if (c == '\n')
 101                NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
 102
 103        NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
 104}
 105
 106void puts(const char *str)
 107{
 108        while (*str)
 109                putc(*str++);
 110}
 111