LXR uboot/arch/arm/cpu/arm926ejs/spear/start.S

   1/*
   2 *  armboot - Startup Code for ARM926EJS CPU-core
   3 *
   4 *  Copyright (c) 2003  Texas Instruments
   5 *
   6 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
   7 *
   8 *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9 *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10 *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
  11 *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12 *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  13 *
  14 * See file CREDITS for list of people who contributed to this
  15 * project.
  16 *
  17 * This program is free software; you can redistribute it and/or
  18 * modify it under the terms of the GNU General Public License as
  19 * published by the Free Software Foundation; either version 2 of
  20 * the License, or (at your option) any later version.
  21 *
  22 * This program is distributed in the hope that it will be useful,
  23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 * GNU General Public License for more details.
  26 *
  27 * You should have received a copy of the GNU General Public License
  28 * along with this program; if not, write to the Free Software
  29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30 * MA 02111-1307 USA
  31 */
  32
  33
  34#include <config.h>
  35
  36.globl _start
  37_start:
  38        b       reset
  39        ldr     pc, _undefined_instruction
  40        ldr     pc, _software_interrupt
  41        ldr     pc, _prefetch_abort
  42        ldr     pc, _data_abort
  43        ldr     pc, _not_used
  44        ldr     pc, _irq
  45        ldr     pc, _fiq
  46
  47_undefined_instruction:
  48_software_interrupt:
  49_prefetch_abort:
  50_data_abort:
  51_not_used:
  52_irq:
  53_fiq:
  54        .word infinite_loop
  55
  56infinite_loop:
  57        b       infinite_loop
  58
  59/*
  60 *************************************************************************
  61 *
  62 * Startup Code (reset vector)
  63 *
  64 * Below are the critical initializations already taken place in BootROM.
  65 * So, these are not taken care in Xloader
  66 * 1. Relocation to RAM
  67 * 2. Initializing stacks
  68 *
  69 *************************************************************************
  70 */
  71
  72/*
  73 * the actual reset code
  74 */
  75
  76reset:
  77/*
  78 * Xloader has to return back to BootROM in a few cases.
  79 * eg. Ethernet boot, UART boot, USB boot
  80 * Saving registers for returning back
  81 */
  82        stmdb   sp!, {r0-r12,r14}
  83        bl      cpu_init_crit
  84/*
  85 * Clearing bss area is not done in Xloader.
  86 * BSS area lies in the DDR location which is not yet initialized
  87 * bss is assumed to be uninitialized.
  88 */
  89        bl      spl_boot
  90        ldmia   sp!, {r0-r12,pc}
  91
  92/*
  93 *************************************************************************
  94 *
  95 * CPU_init_critical registers
  96 *
  97 * setup important registers
  98 * setup memory timing
  99 *
 100 *************************************************************************
 101 */
 102cpu_init_crit:
 103        /*
 104         * flush v4 I/D caches
 105         */
 106        mov     r0, #0
 107        mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 108        mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 109
 110        /*
 111         * enable instruction cache
 112         */
 113        mrc     p15, 0, r0, c1, c0, 0
 114        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
 115        mcr     p15, 0, r0, c1, c0, 0
 116
 117        /*
 118         * Go setup Memory and board specific bits prior to relocation.
 119         */
 120        stmdb   sp!, {lr}
 121        bl      lowlevel_init   /* go setup pll,mux,memory */
 122        ldmia   sp!, {pc}
 123