LXR uboot/arch/m68k/cpu/mcf52x2/cpu

   1/*
   2 * (C) Copyright 2003
   3 * Josef Baumgartner <josef.baumgartner@telex.de>
   4 *
   5 * MCF5282 additionals
   6 * (C) Copyright 2005
   7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
   8 * (c) Copyright 2010
   9 * Arcturus Networks Inc. <www.arcturusnetworks.com>
  10 *
  11 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  12 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  13 * Hayden Fraser (Hayden.Fraser@freescale.com)
  14 *
  15 * MCF5275 additions
  16 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  17 *
  18 * See file CREDITS for list of people who contributed to this
  19 * project.
  20 *
  21 * This program is free software; you can redistribute it and/or
  22 * modify it under the terms of the GNU General Public License as
  23 * published by the Free Software Foundation; either version 2 of
  24 * the License, or (at your option) any later version.
  25 *
  26 * This program is distributed in the hope that it will be useful,
  27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  29 * GNU General Public License for more details.
  30 *
  31 * You should have received a copy of the GNU General Public License
  32 * along with this program; if not, write to the Free Software
  33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  34 * MA 02111-1307 USA
  35 */
  36
  37#include <common.h>
  38#include <watchdog.h>
  39#include <asm/immap.h>
  40#include <asm/io.h>
  41
  42#if defined(CONFIG_CMD_NET)
  43#include <config.h>
  44#include <net.h>
  45#include <asm/fec.h>
  46#endif
  47
  48#ifndef CONFIG_M5272
  49/* Only 5272 Flexbus chipselect is different from the rest */
  50void init_fbcs(void)
  51{
  52        fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
  53
  54#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
  55     && defined(CONFIG_SYS_CS0_CTRL))
  56        out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  57        out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  58        out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  59#else
  60#warning "Chip Select 0 are not initialized/used"
  61#endif
  62#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
  63     && defined(CONFIG_SYS_CS1_CTRL))
  64        out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  65        out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  66        out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  67#endif
  68#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
  69     && defined(CONFIG_SYS_CS2_CTRL))
  70        out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  71        out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  72        out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  73#endif
  74#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
  75     && defined(CONFIG_SYS_CS3_CTRL))
  76        out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  77        out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  78        out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  79#endif
  80#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
  81     && defined(CONFIG_SYS_CS4_CTRL))
  82        out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  83        out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  84        out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  85#endif
  86#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
  87     && defined(CONFIG_SYS_CS5_CTRL))
  88        out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  89        out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  90        out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  91#endif
  92#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
  93     && defined(CONFIG_SYS_CS6_CTRL))
  94        out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
  95        out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
  96        out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
  97#endif
  98#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
  99     && defined(CONFIG_SYS_CS7_CTRL))
 100        out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
 101        out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
 102        out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
 103#endif
 104}
 105#endif
 106
 107#if defined(CONFIG_M5208)
 108void cpu_init_f(void)
 109{
 110        scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
 111
 112#ifndef CONFIG_WATCHDOG
 113        wdog_t *wdg = (wdog_t *) MMAP_WDOG;
 114
 115        /* Disable the watchdog if we aren't using it */
 116        out_be16(&wdg->cr, 0);
 117#endif
 118
 119        out_be32(&scm1->mpr, 0x77777777);
 120        out_be32(&scm1->pacra, 0);
 121        out_be32(&scm1->pacrb, 0);
 122        out_be32(&scm1->pacrc, 0);
 123        out_be32(&scm1->pacrd, 0);
 124        out_be32(&scm1->pacre, 0);
 125        out_be32(&scm1->pacrf, 0);
 126
 127        /* FlexBus Chipselect */
 128        init_fbcs();
 129
 130        icache_enable();
 131}
 132
 133/* initialize higher level parts of CPU like timers */
 134int cpu_init_r(void)
 135{
 136        return (0);
 137}
 138
 139void uart_port_conf(int port)
 140{
 141        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 142
 143        /* Setup Ports: */
 144        switch (port) {
 145        case 0:
 146                clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
 147                setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 148                break;
 149        case 1:
 150                clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
 151                setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
 152                break;
 153        case 2:
 154#ifdef CONFIG_SYS_UART2_PRI_GPIO
 155                clrbits_8(&gpio->par_timer,
 156                        ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
 157                setbits_8(&gpio->par_timer,
 158                        GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 159#endif
 160#ifdef CONFIG_SYS_UART2_ALT1_GPIO
 161                clrbits_8(&gpio->par_feci2c,
 162                        ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
 163                setbits_8(&gpio->par_feci2c,
 164                        GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 165#endif
 166#ifdef CONFIG_SYS_UART2_ALT1_GPIO
 167                clrbits_8(&gpio->par_feci2c,
 168                        ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
 169                setbits_8(&gpio->par_feci2c,
 170                        GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 171#endif
 172                break;
 173        }
 174}
 175
 176#if defined(CONFIG_CMD_NET)
 177int fecpin_setclear(struct eth_device *dev, int setclear)
 178{
 179        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 180
 181        if (setclear) {
 182                setbits_8(&gpio->par_fec,
 183                        GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
 184                setbits_8(&gpio->par_feci2c,
 185                        GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
 186        } else {
 187                clrbits_8(&gpio->par_fec,
 188                        ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
 189                clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
 190        }
 191        return 0;
 192}
 193#endif                          /* CONFIG_CMD_NET */
 194#endif                          /* CONFIG_M5208 */
 195
 196#if defined(CONFIG_M5253)
 197/*
 198 * Breath some life into the CPU...
 199 *
 200 * Set up the memory map,
 201 * initialize a bunch of registers,
 202 * initialize the UPM's
 203 */
 204void cpu_init_f(void)
 205{
 206        mbar_writeByte(MCFSIM_MPARK, 0x40);     /* 5249 Internal Core takes priority over DMA */
 207        mbar_writeByte(MCFSIM_SYPCR, 0x00);
 208        mbar_writeByte(MCFSIM_SWIVR, 0x0f);
 209        mbar_writeByte(MCFSIM_SWSR, 0x00);
 210        mbar_writeByte(MCFSIM_SWDICR, 0x00);
 211        mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
 212        mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
 213        mbar_writeByte(MCFSIM_I2CICR, 0x00);
 214        mbar_writeByte(MCFSIM_UART1ICR, 0x00);
 215        mbar_writeByte(MCFSIM_UART2ICR, 0x00);
 216        mbar_writeByte(MCFSIM_ICR6, 0x00);
 217        mbar_writeByte(MCFSIM_ICR7, 0x00);
 218        mbar_writeByte(MCFSIM_ICR8, 0x00);
 219        mbar_writeByte(MCFSIM_ICR9, 0x00);
 220        mbar_writeByte(MCFSIM_QSPIICR, 0x00);
 221
 222        mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
 223        mbar2_writeByte(MCFSIM_INTBASE, 0x40);  /* Base interrupts at 64 */
 224        mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 225
 226        /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
 227
 228        /* FlexBus Chipselect */
 229        init_fbcs();
 230
 231#ifdef CONFIG_FSL_I2C
 232        CONFIG_SYS_I2C_PINMUX_REG =
 233            CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
 234        CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 235#ifdef CONFIG_SYS_I2C2_OFFSET
 236        CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
 237        CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
 238#endif
 239#endif
 240
 241        /* enable instruction cache now */
 242        icache_enable();
 243}
 244
 245/*initialize higher level parts of CPU like timers */
 246int cpu_init_r(void)
 247{
 248        return (0);
 249}
 250
 251void uart_port_conf(int port)
 252{
 253        u32 *par = (u32 *) MMAP_PAR;
 254
 255        /* Setup Ports: */
 256        switch (port) {
 257        case 1:
 258                clrbits_be32(par, 0x00180000);
 259                setbits_be32(par, 0x00180000);
 260                break;
 261        case 2:
 262                clrbits_be32(par, 0x00000003);
 263                clrbits_be32(par, 0xFFFFFFFC);
 264                break;
 265        }
 266}
 267#endif                          /* #if defined(CONFIG_M5253) */
 268
 269#if defined(CONFIG_M5271)
 270void cpu_init_f(void)
 271{
 272#ifndef CONFIG_WATCHDOG
 273        /* Disable the watchdog if we aren't using it */
 274        mbar_writeShort(MCF_WTM_WCR, 0);
 275#endif
 276
 277        /* FlexBus Chipselect */
 278        init_fbcs();
 279
 280#ifdef CONFIG_SYS_MCF_SYNCR
 281        /* Set clockspeed according to board header file */
 282        mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
 283#else
 284        /* Set clockspeed to 100MHz */
 285        mbar_writeLong(MCF_FMPLL_SYNCR,
 286                        MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
 287#endif
 288        while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ;
 289}
 290
 291/*
 292 * initialize higher level parts of CPU like timers
 293 */
 294int cpu_init_r(void)
 295{
 296        return (0);
 297}
 298
 299void uart_port_conf(int port)
 300{
 301        u16 temp;
 302
 303        /* Setup Ports: */
 304        switch (port) {
 305        case 0:
 306                temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
 307                temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
 308                mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 309                break;
 310        case 1:
 311                temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
 312                temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
 313                mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 314                break;
 315        case 2:
 316                temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
 317                temp |= (0x3000);
 318                mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 319                break;
 320        }
 321}
 322
 323#if defined(CONFIG_CMD_NET)
 324int fecpin_setclear(struct eth_device *dev, int setclear)
 325{
 326        if (setclear) {
 327                /* Enable Ethernet pins */
 328                mbar_writeByte(MCF_GPIO_PAR_FECI2C,
 329                               (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
 330        } else {
 331        }
 332
 333        return 0;
 334}
 335#endif                          /* CONFIG_CMD_NET */
 336
 337#if defined(CONFIG_CF_QSPI)
 338
 339/* Configure PIOs for SIN, SOUT, and SCK */
 340void cfspi_port_conf(void)
 341{
 342        mbar_writeByte(MCF_GPIO_PAR_QSPI,
 343                       MCF_GPIO_PAR_QSPI_SIN_SIN   |
 344                       MCF_GPIO_PAR_QSPI_SOUT_SOUT |
 345                       MCF_GPIO_PAR_QSPI_SCK_SCK);
 346}
 347#endif                          /* CONFIG_CF_QSPI */
 348
 349#endif                          /* CONFIG_M5271 */
 350
 351#if defined(CONFIG_M5272)
 352/*
 353 * Breath some life into the CPU...
 354 *
 355 * Set up the memory map,
 356 * initialize a bunch of registers,
 357 * initialize the UPM's
 358 */
 359void cpu_init_f(void)
 360{
 361        /* if we come from RAM we assume the CPU is
 362         * already initialized.
 363         */
 364#ifndef CONFIG_MONITOR_IS_IN_RAM
 365        sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
 366        gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
 367        csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
 368
 369        out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
 370        out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
 371
 372        /* Setup Ports: */
 373        out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
 374        out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
 375        out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
 376        out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
 377        out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
 378        out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
 379        out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
 380
 381        /* Memory Controller: */
 382        out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
 383        out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
 384
 385#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
 386        out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
 387        out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
 388#endif
 389
 390#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 391        out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
 392        out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
 393#endif
 394
 395#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
 396        out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
 397        out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
 398#endif
 399
 400#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
 401        out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
 402        out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
 403#endif
 404
 405#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
 406        out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
 407        out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
 408#endif
 409
 410#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
 411        out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
 412        out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
 413#endif
 414
 415#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
 416        out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
 417        out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
 418#endif
 419
 420#endif                          /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 421
 422        /* enable instruction cache now */
 423        icache_enable();
 424
 425}
 426
 427/*
 428 * initialize higher level parts of CPU like timers
 429 */
 430int cpu_init_r(void)
 431{
 432        return (0);
 433}
 434
 435void uart_port_conf(int port)
 436{
 437        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 438
 439        /* Setup Ports: */
 440        switch (port) {
 441        case 0:
 442                clrbits_be32(&gpio->gpio_pbcnt,
 443                        GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
 444                setbits_be32(&gpio->gpio_pbcnt,
 445                        GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
 446                break;
 447        case 1:
 448                clrbits_be32(&gpio->gpio_pdcnt,
 449                        GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
 450                setbits_be32(&gpio->gpio_pdcnt,
 451                        GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
 452                break;
 453        }
 454}
 455
 456#if defined(CONFIG_CMD_NET)
 457int fecpin_setclear(struct eth_device *dev, int setclear)
 458{
 459        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 460
 461        if (setclear) {
 462                setbits_be32(&gpio->gpio_pbcnt,
 463                        GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
 464                        GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
 465                        GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
 466                        GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
 467        } else {
 468        }
 469        return 0;
 470}
 471#endif                          /* CONFIG_CMD_NET */
 472#endif                          /* #if defined(CONFIG_M5272) */
 473
 474#if defined(CONFIG_M5275)
 475
 476/*
 477 * Breathe some life into the CPU...
 478 *
 479 * Set up the memory map,
 480 * initialize a bunch of registers,
 481 * initialize the UPM's
 482 */
 483void cpu_init_f(void)
 484{
 485        /*
 486         * if we come from RAM we assume the CPU is
 487         * already initialized.
 488         */
 489
 490#ifndef CONFIG_MONITOR_IS_IN_RAM
 491        wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
 492        gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
 493
 494        /* Kill watchdog so we can initialize the PLL */
 495        out_be16(&wdog_reg->wcr, 0);
 496
 497        /* FlexBus Chipselect */
 498        init_fbcs();
 499#endif                          /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 500
 501#ifdef CONFIG_FSL_I2C
 502        CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
 503        CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 504#endif
 505
 506        /* enable instruction cache now */
 507        icache_enable();
 508}
 509
 510/*
 511 * initialize higher level parts of CPU like timers
 512 */
 513int cpu_init_r(void)
 514{
 515        return (0);
 516}
 517
 518void uart_port_conf(int port)
 519{
 520        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 521
 522        /* Setup Ports: */
 523        switch (port) {
 524        case 0:
 525                clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
 526                setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
 527                break;
 528        case 1:
 529                clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
 530                setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
 531                break;
 532        case 2:
 533                clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
 534                setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
 535                break;
 536        }
 537}
 538
 539#if defined(CONFIG_CMD_NET)
 540int fecpin_setclear(struct eth_device *dev, int setclear)
 541{
 542        struct fec_info_s *info = (struct fec_info_s *) dev->priv;
 543        gpio_t *gpio = (gpio_t *)MMAP_GPIO;
 544
 545        if (setclear) {
 546                /* Enable Ethernet pins */
 547                if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 548                        setbits_be16(&gpio->par_feci2c, 0x0f00);
 549                        setbits_8(&gpio->par_fec0hl, 0xc0);
 550                } else {
 551                        setbits_be16(&gpio->par_feci2c, 0x00a0);
 552                        setbits_8(&gpio->par_fec1hl, 0xc0);
 553                }
 554        } else {
 555                if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 556                        clrbits_be16(&gpio->par_feci2c, 0x0f00);
 557                        clrbits_8(&gpio->par_fec0hl, 0xc0);
 558                } else {
 559                        clrbits_be16(&gpio->par_feci2c, 0x00a0);
 560                        clrbits_8(&gpio->par_fec1hl, 0xc0);
 561                }
 562        }
 563
 564        return 0;
 565}
 566#endif                          /* CONFIG_CMD_NET */
 567#endif                          /* #if defined(CONFIG_M5275) */
 568
 569#if defined(CONFIG_M5282)
 570/*
 571 * Breath some life into the CPU...
 572 *
 573 * Set up the memory map,
 574 * initialize a bunch of registers,
 575 * initialize the UPM's
 576 */
 577void cpu_init_f(void)
 578{
 579#ifndef CONFIG_WATCHDOG
 580        /* disable watchdog if we aren't using it */
 581        MCFWTM_WCR = 0;
 582#endif
 583
 584#ifndef CONFIG_MONITOR_IS_IN_RAM
 585        /* Set speed /PLL */
 586        MCFCLOCK_SYNCR =
 587            MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
 588            MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
 589        while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
 590
 591        MCFGPIO_PBCDPAR = 0xc0;
 592
 593        /* Set up the GPIO ports */
 594#ifdef CONFIG_SYS_PEPAR
 595        MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
 596#endif
 597#ifdef  CONFIG_SYS_PFPAR
 598        MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
 599#endif
 600#ifdef CONFIG_SYS_PJPAR
 601        MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
 602#endif
 603#ifdef CONFIG_SYS_PSDPAR
 604        MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
 605#endif
 606#ifdef CONFIG_SYS_PASPAR
 607        MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
 608#endif
 609#ifdef CONFIG_SYS_PEHLPAR
 610        MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 611#endif
 612#ifdef CONFIG_SYS_PQSPAR
 613        MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
 614#endif
 615#ifdef CONFIG_SYS_PTCPAR
 616        MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
 617#endif
 618#if defined(CONFIG_SYS_PORTTC)
 619        MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
 620#endif
 621#if defined(CONFIG_SYS_DDRTC)
 622        MCFGPIO_DDRTC  = CONFIG_SYS_DDRTC;
 623#endif
 624#ifdef CONFIG_SYS_PTDPAR
 625        MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
 626#endif
 627#ifdef CONFIG_SYS_PUAPAR
 628        MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
 629#endif
 630
 631#if defined(CONFIG_SYS_DDRD)
 632        MCFGPIO_DDRD = CONFIG_SYS_DDRD;
 633#endif
 634#ifdef CONFIG_SYS_DDRUA
 635        MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
 636#endif
 637
 638        /* FlexBus Chipselect */
 639        init_fbcs();
 640
 641#endif                          /* CONFIG_MONITOR_IS_IN_RAM */
 642
 643        /* defer enabling cache until boot (see do_go) */
 644        /* icache_enable(); */
 645}
 646
 647/*
 648 * initialize higher level parts of CPU like timers
 649 */
 650int cpu_init_r(void)
 651{
 652        return (0);
 653}
 654
 655void uart_port_conf(int port)
 656{
 657        /* Setup Ports: */
 658        switch (port) {
 659        case 0:
 660                MCFGPIO_PUAPAR &= 0xFc;
 661                MCFGPIO_PUAPAR |= 0x03;
 662                break;
 663        case 1:
 664                MCFGPIO_PUAPAR &= 0xF3;
 665                MCFGPIO_PUAPAR |= 0x0C;
 666                break;
 667        case 2:
 668                MCFGPIO_PASPAR &= 0xFF0F;
 669                MCFGPIO_PASPAR |= 0x00A0;
 670                break;
 671        }
 672}
 673
 674#if defined(CONFIG_CMD_NET)
 675int fecpin_setclear(struct eth_device *dev, int setclear)
 676{
 677        if (setclear) {
 678                MCFGPIO_PASPAR |= 0x0F00;
 679                MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 680        } else {
 681                MCFGPIO_PASPAR &= 0xF0FF;
 682                MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
 683        }
 684        return 0;
 685}
 686#endif                  /* CONFIG_CMD_NET */
 687#endif
 688
 689#if defined(CONFIG_M5249)
 690/*
 691 * Breath some life into the CPU...
 692 *
 693 * Set up the memory map,
 694 * initialize a bunch of registers,
 695 * initialize the UPM's
 696 */
 697void cpu_init_f(void)
 698{
 699        /*
 700         *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
 701         *        (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
 702         *        which is their primary function.
 703         *        ~Jeremy
 704         */
 705        mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
 706        mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
 707        mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
 708        mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
 709        mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
 710        mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
 711
 712        /*
 713         *  dBug Compliance:
 714         *    You can verify these values by using dBug's 'ird'
 715         *    (Internal Register Display) command
 716         *    ~Jeremy
 717         *
 718         */
 719        mbar_writeByte(MCFSIM_MPARK, 0x30);     /* 5249 Internal Core takes priority over DMA */
 720        mbar_writeByte(MCFSIM_SYPCR, 0x00);
 721        mbar_writeByte(MCFSIM_SWIVR, 0x0f);
 722        mbar_writeByte(MCFSIM_SWSR, 0x00);
 723        mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
 724        mbar_writeByte(MCFSIM_SWDICR, 0x00);
 725        mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
 726        mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
 727        mbar_writeByte(MCFSIM_I2CICR, 0x00);
 728        mbar_writeByte(MCFSIM_UART1ICR, 0x00);
 729        mbar_writeByte(MCFSIM_UART2ICR, 0x00);
 730        mbar_writeByte(MCFSIM_ICR6, 0x00);
 731        mbar_writeByte(MCFSIM_ICR7, 0x00);
 732        mbar_writeByte(MCFSIM_ICR8, 0x00);
 733        mbar_writeByte(MCFSIM_ICR9, 0x00);
 734        mbar_writeByte(MCFSIM_QSPIICR, 0x00);
 735
 736        mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
 737        mbar2_writeByte(MCFSIM_INTBASE, 0x40);  /* Base interrupts at 64 */
 738        mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 739        mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
 740
 741        /* Setup interrupt priorities for gpio7 */
 742        /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
 743
 744        /* IDE Config registers */
 745        mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
 746        mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
 747
 748        /* FlexBus Chipselect */
 749        init_fbcs();
 750
 751        /* enable instruction cache now */
 752        icache_enable();
 753}
 754
 755/*
 756 * initialize higher level parts of CPU like timers
 757 */
 758int cpu_init_r(void)
 759{
 760        return (0);
 761}
 762
 763void uart_port_conf(int port)
 764{
 765}
 766#endif                          /* #if defined(CONFIG_M5249) */
 767