1/* 2 * (C) Copyright 2007-2009 DENX Software Engineering 3 * 4 * MPC512x Internal Memory Map 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 * 21 * Based on the MPC83xx header. 22 */ 23 24#ifndef __IMMAP_512x__ 25#define __IMMAP_512x__ 26 27#include <asm/types.h> 28#if defined(CONFIG_E300) 29#include <asm/e300.h> 30#endif 31 32/* 33 * System reset offset (PowerPC standard) 34 */ 35#define EXC_OFF_SYS_RESET 0x0100 36#define _START_OFFSET EXC_OFF_SYS_RESET 37 38#define SPR_5121E 0x80180000 39 40/* 41 * IMMRBAR - Internal Memory Register Base Address 42 */ 43#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 44#define IMMRBAR 0x0000 /* Register offset to immr */ 45#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 46#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 47 48 49#ifndef __ASSEMBLY__ 50typedef struct law512x { 51 u32 bar; /* Base Addr Register */ 52 u32 ar; /* Attributes Register */ 53} law512x_t; 54 55/* 56 * System configuration registers 57 */ 58typedef struct sysconf512x { 59 u32 immrbar; /* Internal memory map base address register */ 60 u8 res0[0x1c]; 61 u32 lpbaw; /* LP Boot Access Window */ 62 u32 lpcs0aw; /* LP CS0 Access Window */ 63 u32 lpcs1aw; /* LP CS1 Access Window */ 64 u32 lpcs2aw; /* LP CS2 Access Window */ 65 u32 lpcs3aw; /* LP CS3 Access Window */ 66 u32 lpcs4aw; /* LP CS4 Access Window */ 67 u32 lpcs5aw; /* LP CS5 Access Window */ 68 u32 lpcs6aw; /* LP CS6 Access Window */ 69 u32 lpcs7aw; /* LP CS7 Access Window */ 70 u8 res1[0x1c]; 71 law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ 72 u8 res2[0x28]; 73 law512x_t ddrlaw; /* DDR Local Access Window */ 74 u8 res3[0x18]; 75 u32 mbxbar; /* MBX Base Address */ 76 u32 srambar; /* SRAM Base Address */ 77 u32 nfcbar; /* NFC Base Address */ 78 u8 res4[0x34]; 79 u32 spridr; /* System Part and Revision ID Register */ 80 u32 spcr; /* System Priority Configuration Register */ 81 u8 res5[0xf8]; 82} sysconf512x_t; 83 84#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 85 86/* 87 * Watch Dog Timer (WDT) Registers 88 */ 89typedef struct wdt512x { 90 u8 res0[4]; 91 u32 swcrr; /* System watchdog control register */ 92 u32 swcnr; /* System watchdog count register */ 93 u8 res1[2]; 94 u16 swsrr; /* System watchdog service register */ 95 u8 res2[0xF0]; 96} wdt512x_t; 97 98/* 99 * RTC Module Registers 100 */ 101typedef struct rtclk512x { 102 u8 fixme[0x100]; 103} rtclk512x_t; 104 105/* 106 * General Purpose Timer 107 */ 108typedef struct gpt512x { 109 u8 fixme[0x100]; 110} gpt512x_t; 111 112/* 113 * Integrated Programmable Interrupt Controller 114 */ 115typedef struct ipic512x { 116 u8 fixme[0x100]; 117} ipic512x_t; 118 119/* 120 * System Arbiter Registers 121 */ 122typedef struct arbiter512x { 123 u32 acr; /* Arbiter Configuration Register */ 124 u32 atr; /* Arbiter Timers Register */ 125 u32 ater; /* Arbiter Transfer Error Register */ 126 u32 aer; /* Arbiter Event Register */ 127 u32 aidr; /* Arbiter Interrupt Definition Register */ 128 u32 amr; /* Arbiter Mask Register */ 129 u32 aeatr; /* Arbiter Event Attributes Register */ 130 u32 aeadr; /* Arbiter Event Address Register */ 131 u32 aerr; /* Arbiter Event Response Register */ 132 u8 res1[0xDC]; 133} arbiter512x_t; 134 135/* 136 * Reset Module 137 */ 138typedef struct reset512x { 139 u32 rcwl; /* Reset Configuration Word Low Register */ 140 u32 rcwh; /* Reset Configuration Word High Register */ 141 u8 res0[8]; 142 u32 rsr; /* Reset Status Register */ 143 u32 rmr; /* Reset Mode Register */ 144 u32 rpr; /* Reset protection Register */ 145 u32 rcr; /* Reset Control Register */ 146 u32 rcer; /* Reset Control Enable Register */ 147 u8 res1[0xDC]; 148} reset512x_t; 149 150/* RSR - Reset Status Register */ 151#define RSR_SWSR 0x00002000 /* software soft reset */ 152#define RSR_SWHR 0x00001000 /* software hard reset */ 153#define RSR_JHRS 0x00000200 /* jtag hreset */ 154#define RSR_JSRS 0x00000100 /* jtag sreset status */ 155#define RSR_CSHR 0x00000010 /* checkstop reset status */ 156#define RSR_SWRS 0x00000008 /* software watchdog reset status */ 157#define RSR_BMRS 0x00000004 /* bus monitop reset status */ 158#define RSR_SRS 0x00000002 /* soft reset status */ 159#define RSR_HRS 0x00000001 /* hard reset status */ 160#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\ 161 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 162 RSR_BMRS | RSR_SRS | RSR_HRS) 163 164/* RMR - Reset Mode Register */ 165#define RMR_CSRE 0x00000001 /* checkstop reset enable */ 166#define RMR_CSRE_SHIFT 0 167#define RMR_RES (~(RMR_CSRE)) 168 169/* RCR - Reset Control Register */ 170#define RCR_SWHR 0x00000002 /* software hard reset */ 171#define RCR_SWSR 0x00000001 /* software soft reset */ 172#define RCR_RES (~(RCR_SWHR | RCR_SWSR)) 173 174/* RCER - Reset Control Enable Register */ 175#define RCER_CRE 0x00000001 /* software hard reset */ 176#define RCER_RES (~(RCER_CRE)) 177 178/* 179 * Clock Module 180 */ 181typedef struct clk512x { 182 u32 spmr; /* System PLL Mode Register */ 183 u32 sccr[2]; /* System Clock Control Registers */ 184 u32 scfr[2]; /* System Clock Frequency Registers */ 185 u8 res0[4]; 186 u32 bcr; /* Bread Crumb Register */ 187 u32 pscccr[12]; /* PSC0-11 Clock Control Registers */ 188 u32 spccr; /* SPDIF Clock Control Register */ 189 u32 cccr; /* CFM Clock Control Register */ 190 u32 dccr; /* DIU Clock Control Register */ 191 u32 msccr[4]; /* MSCAN1-4 Clock Control Registers */ 192 u8 res1[0x98]; 193} clk512x_t; 194 195/* SPMR - System PLL Mode Register */ 196#define SPMR_SPMF 0x0F000000 197#define SPMR_SPMF_SHIFT 24 198#define SPMR_CPMF 0x000F0000 199#define SPMR_CPMF_SHIFT 16 200 201/* System Clock Control Register 1 commands */ 202#define CLOCK_SCCR1_CFG_EN 0x80000000 203#define CLOCK_SCCR1_LPC_EN 0x40000000 204#define CLOCK_SCCR1_NFC_EN 0x20000000 205#define CLOCK_SCCR1_PATA_EN 0x10000000 206#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) 207#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 208#define CLOCK_SCCR1_SATA_EN 0x00004000 209#define CLOCK_SCCR1_FEC_EN 0x00002000 210#define CLOCK_SCCR1_TPR_EN 0x00001000 211#define CLOCK_SCCR1_PCI_EN 0x00000800 212#define CLOCK_SCCR1_DDR_EN 0x00000400 213 214/* System Clock Control Register 2 commands */ 215#define CLOCK_SCCR2_DIU_EN 0x80000000 216#define CLOCK_SCCR2_AXE_EN 0x40000000 217#define CLOCK_SCCR2_MEM_EN 0x20000000 218#define CLOCK_SCCR2_USB1_EN 0x10000000 219#define CLOCK_SCCR2_USB2_EN 0x08000000 220#define CLOCK_SCCR2_I2C_EN 0x04000000 221#define CLOCK_SCCR2_BDLC_EN 0x02000000 222#define CLOCK_SCCR2_SDHC_EN 0x01000000 223#define CLOCK_SCCR2_SPDIF_EN 0x00800000 224#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 225#define CLOCK_SCCR2_MBX_EN 0x00200000 226#define CLOCK_SCCR2_MBX_3D_EN 0x00100000 227#define CLOCK_SCCR2_IIM_EN 0x00080000 228 229/* SCFR1 System Clock Frequency Register 1 */ 230#ifndef SCFR1_IPS_DIV 231#define SCFR1_IPS_DIV 0x3 232#endif 233#define SCFR1_IPS_DIV_MASK 0x03800000 234#define SCFR1_IPS_DIV_SHIFT 23 235 236#define SCFR1_PCI_DIV 0x6 237#define SCFR1_PCI_DIV_MASK 0x00700000 238#define SCFR1_PCI_DIV_SHIFT 20 239 240#define SCFR1_LPC_DIV_MASK 0x00003800 241#define SCFR1_LPC_DIV_SHIFT 11 242 243#define SCFR1_NFC_DIV_MASK 0x00000700 244#define SCFR1_NFC_DIV_SHIFT 8 245 246#define SCFR1_DIU_DIV_MASK 0x000000FF 247#define SCFR1_DIU_DIV_SHIFT 0 248 249/* SCFR2 System Clock Frequency Register 2 */ 250#define SCFR2_SYS_DIV 0xFC000000 251#define SCFR2_SYS_DIV_SHIFT 26 252 253/* SPCR - System Priority Configuration Register */ 254#define SPCR_TBEN 0x00400000 /* E300 core time base unit enable */ 255 256/* 257 * Power Management Control Module 258 */ 259typedef struct pmc512x { 260 u8 fixme[0x100]; 261} pmc512x_t; 262 263/* 264 * General purpose I/O module 265 */ 266typedef struct gpio512x { 267 u32 gpdir; 268 u32 gpodr; 269 u32 gpdat; 270 u32 gpier; 271 u32 gpimr; 272 u32 gpicr1; 273 u32 gpicr2; 274 u8 res0[0xE4]; 275} gpio512x_t; 276 277/* 278 * DDR Memory Controller Memory Map 279 */ 280typedef struct ddr512x { 281 u32 ddr_sys_config; /* System Configuration Register */ 282 u32 ddr_time_config0; /* Timing Configuration Register */ 283 u32 ddr_time_config1; /* Timing Configuration Register */ 284 u32 ddr_time_config2; /* Timing Configuration Register */ 285 u32 ddr_command; /* Command Register */ 286 u32 ddr_compact_command; /* Compact Command Register */ 287 u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */ 288 u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */ 289 u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */ 290 u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */ 291 u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */ 292 u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ 293 u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ 294 u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ 295 u32 DQS_config_offset_count; /* DQS Config Offset Count */ 296 u32 DQS_config_offset_time; /* DQS Config Offset Time */ 297 u32 DQS_delay_status; /* DQS Delay Status */ 298 u32 res0[0xF]; 299 u32 prioman_config1; /* Priority Manager Configuration */ 300 u32 prioman_config2; /* Priority Manager Configuration */ 301 u32 hiprio_config; /* High Priority Configuration */ 302 u32 lut_table0_main_upper; /* LUT0 Main Upper */ 303 u32 lut_table1_main_upper; /* LUT1 Main Upper */ 304 u32 lut_table2_main_upper; /* LUT2 Main Upper */ 305 u32 lut_table3_main_upper; /* LUT3 Main Upper */ 306 u32 lut_table4_main_upper; /* LUT4 Main Upper */ 307 u32 lut_table0_main_lower; /* LUT0 Main Lower */ 308 u32 lut_table1_main_lower; /* LUT1 Main Lower */ 309 u32 lut_table2_main_lower; /* LUT2 Main Lower */ 310 u32 lut_table3_main_lower; /* LUT3 Main Lower */ 311 u32 lut_table4_main_lower; /* LUT4 Main Lower */ 312 u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */ 313 u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */ 314 u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */ 315 u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */ 316 u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */ 317 u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */ 318 u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */ 319 u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */ 320 u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */ 321 u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */ 322 u32 performance_monitor_config; 323 u32 event_time_counter; 324 u32 event_time_preset; 325 u32 performance_monitor1_address_low; 326 u32 performance_monitor2_address_low; 327 u32 performance_monitor1_address_hi; 328 u32 performance_monitor2_address_hi; 329 u32 res1[2]; 330 u32 performance_monitor1_read_counter; 331 u32 performance_monitor2_read_counter; 332 u32 performance_monitor1_write_counter; 333 u32 performance_monitor2_write_counter; 334 u32 granted_ack_counter0; 335 u32 granted_ack_counter1; 336 u32 granted_ack_counter2; 337 u32 granted_ack_counter3; 338 u32 granted_ack_counter4; 339 u32 cumulative_wait_counter0; 340 u32 cumulative_wait_counter1; 341 u32 cumulative_wait_counter2; 342 u32 cumulative_wait_counter3; 343 u32 cumulative_wait_counter4; 344 u32 summed_priority_counter0; 345 u32 summed_priority_counter1; 346 u32 summed_priority_counter2; 347 u32 summed_priority_counter3; 348 u32 summed_priority_counter4; 349 u32 res2[0x3AD]; 350} ddr512x_t; 351 352/* MDDRC SYS CFG and Timing CFG0 Registers */ 353#define MDDRC_SYS_CFG_EN 0xF0000000 354#define MDDRC_SYS_CFG_CKE_MASK 0x40000000 355#define MDDRC_SYS_CFG_CMD_MASK 0x10000000 356#define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF 357 358/* 359 * DDR Memory Controller Configuration settings 360 */ 361typedef struct ddr512x_config { 362 u32 ddr_sys_config; /* System Configuration Register */ 363 u32 ddr_time_config0; /* Timing Configuration Register */ 364 u32 ddr_time_config1; /* Timing Configuration Register */ 365 u32 ddr_time_config2; /* Timing Configuration Register */ 366} ddr512x_config_t; 367 368typedef struct sdram_conf_s { 369 unsigned long size; 370 ddr512x_config_t cfg; 371} sdram_conf_t; 372 373/* 374 * DMA/Messaging Unit 375 */ 376typedef struct dma512x { 377 u8 fixme[0x1800]; 378} dma512x_t; 379 380/* 381 * PCI Software Configuration Registers 382 */ 383typedef struct pciconf512x { 384 u32 config_address; 385 u32 config_data; 386 u32 int_ack; 387 u8 res[116]; 388} pciconf512x_t; 389 390/* 391 * PCI Outbound Translation Register 392 */ 393typedef struct pci_outbound_window { 394 u32 potar; 395 u8 res0[4]; 396 u32 pobar; 397 u8 res1[4]; 398 u32 pocmr; 399 u8 res2[4]; 400} pot512x_t; 401 402/* POTAR - PCI Outbound Translation Address Register */ 403#define POTAR_TA_MASK 0x000fffff 404 405/* POBAR - PCI Outbound Base Address Register */ 406#define POBAR_BA_MASK 0x000fffff 407 408/* POCMR - PCI Outbound Comparision Mask Register */ 409#define POCMR_EN 0x80000000 410#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 411#define POCMR_PRE 0x20000000 /* prefetch enable */ 412#define POCMR_SBS 0x00100000 /* special byte swap enable */ 413#define POCMR_CM_MASK 0x000fffff 414#define POCMR_CM_4G 0x00000000 415#define POCMR_CM_2G 0x00080000 416#define POCMR_CM_1G 0x000C0000 417#define POCMR_CM_512M 0x000E0000 418#define POCMR_CM_256M 0x000F0000 419#define POCMR_CM_128M 0x000F8000 420#define POCMR_CM_64M 0x000FC000 421#define POCMR_CM_32M 0x000FE000 422#define POCMR_CM_16M 0x000FF000 423#define POCMR_CM_8M 0x000FF800 424#define POCMR_CM_4M 0x000FFC00 425#define POCMR_CM_2M 0x000FFE00 426#define POCMR_CM_1M 0x000FFF00 427#define POCMR_CM_512K 0x000FFF80 428#define POCMR_CM_256K 0x000FFFC0 429#define POCMR_CM_128K 0x000FFFE0 430#define POCMR_CM_64K 0x000FFFF0 431#define POCMR_CM_32K 0x000FFFF8 432#define POCMR_CM_16K 0x000FFFFC 433#define POCMR_CM_8K 0x000FFFFE 434#define POCMR_CM_4K 0x000FFFFF 435 436/* 437 * Sequencer 438 */ 439typedef struct ios512x { 440 pot512x_t pot[6]; 441 u8 res0[0x60]; 442 u32 pmcr; 443 u8 res1[4]; 444 u32 dtcr; 445 u8 res2[4]; 446} ios512x_t; 447 448/* 449 * PCI Controller 450 */ 451typedef struct pcictrl512x { 452 u32 esr; 453 u32 ecdr; 454 u32 eer; 455 u32 eatcr; 456 u32 eacr; 457 u32 eeacr; 458 u32 edlcr; 459 u32 edhcr; 460 u32 gcr; 461 u32 ecr; 462 u32 gsr; 463 u8 res0[12]; 464 u32 pitar2; 465 u8 res1[4]; 466 u32 pibar2; 467 u32 piebar2; 468 u32 piwar2; 469 u8 res2[4]; 470 u32 pitar1; 471 u8 res3[4]; 472 u32 pibar1; 473 u32 piebar1; 474 u32 piwar1; 475 u8 res4[4]; 476 u32 pitar0; 477 u8 res5[4]; 478 u32 pibar0; 479 u8 res6[4]; 480 u32 piwar0; 481 u8 res7[132]; 482} pcictrl512x_t; 483 484 485/* PITAR - PCI Inbound Translation Address Register 486 */ 487#define PITAR_TA_MASK 0x000fffff 488 489/* PIBAR - PCI Inbound Base/Extended Address Register 490 */ 491#define PIBAR_MASK 0xffffffff 492#define PIEBAR_EBA_MASK 0x000fffff 493 494/* PIWAR - PCI Inbound Windows Attributes Register 495 */ 496#define PIWAR_EN 0x80000000 497#define PIWAR_SBS 0x40000000 498#define PIWAR_PF 0x20000000 499#define PIWAR_RTT_MASK 0x000f0000 500#define PIWAR_RTT_NO_SNOOP 0x00040000 501#define PIWAR_RTT_SNOOP 0x00050000 502#define PIWAR_WTT_MASK 0x0000f000 503#define PIWAR_WTT_NO_SNOOP 0x00004000 504#define PIWAR_WTT_SNOOP 0x00005000 505 506/* 507 * MSCAN 508 */ 509typedef struct mscan512x { 510 u8 fixme[0x100]; 511} mscan512x_t; 512 513/* 514 * BDLC 515 */ 516typedef struct bdlc512x { 517 u8 fixme[0x100]; 518} bdlc512x_t; 519 520/* 521 * SDHC 522 */ 523typedef struct sdhc512x { 524 u8 fixme[0x100]; 525} sdhc512x_t; 526 527/* 528 * SPDIF 529 */ 530typedef struct spdif512x { 531 u8 fixme[0x100]; 532} spdif512x_t; 533 534/* 535 * I2C 536 */ 537typedef struct i2c512x_dev { 538 volatile u32 madr; /* I2Cn + 0x00 */ 539 volatile u32 mfdr; /* I2Cn + 0x04 */ 540 volatile u32 mcr; /* I2Cn + 0x08 */ 541 volatile u32 msr; /* I2Cn + 0x0C */ 542 volatile u32 mdr; /* I2Cn + 0x10 */ 543 u8 res0[0x0C]; 544} i2c512x_dev_t; 545 546/* Number of I2C buses */ 547#define I2C_BUS_CNT 3 548 549typedef struct i2c512x { 550 i2c512x_dev_t dev[I2C_BUS_CNT]; 551 volatile u32 icr; 552 volatile u32 mifr; 553 u8 res0[0x98]; 554} i2c512x_t; 555 556/* I2Cn control register bits */ 557#define I2C_EN 0x80 558#define I2C_IEN 0x40 559#define I2C_STA 0x20 560#define I2C_TX 0x10 561#define I2C_TXAK 0x08 562#define I2C_RSTA 0x04 563#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) 564 565/* I2Cn status register bits */ 566#define I2C_CF 0x80 567#define I2C_AAS 0x40 568#define I2C_BB 0x20 569#define I2C_AL 0x10 570#define I2C_SRW 0x04 571#define I2C_IF 0x02 572#define I2C_RXAK 0x01 573 574/* 575 * AXE 576 */ 577typedef struct axe512x { 578 u8 fixme[0x100]; 579} axe512x_t; 580 581/* 582 * DIU 583 */ 584typedef struct diu512x { 585 u8 fixme[0x100]; 586} diu512x_t; 587 588/* 589 * CFM 590 */ 591typedef struct cfm512x { 592 u8 fixme[0x100]; 593} cfm512x_t; 594 595/* 596 * FEC 597 */ 598typedef struct fec512x { 599 u32 fec_id; /* FEC_ID register */ 600 u32 ievent; /* Interrupt event register */ 601 u32 imask; /* Interrupt mask register */ 602 u32 reserved_01; 603 u32 r_des_active; /* Receive ring updated flag */ 604 u32 x_des_active; /* Transmit ring updated flag */ 605 u32 reserved_02[3]; 606 u32 ecntrl; /* Ethernet control register */ 607 u32 reserved_03[6]; 608 u32 mii_data; /* MII data register */ 609 u32 mii_speed; /* MII speed register */ 610 u32 reserved_04[7]; 611 u32 mib_control; /* MIB control/status register */ 612 u32 reserved_05[7]; 613 u32 r_cntrl; /* Receive control register */ 614 u32 r_hash; /* Receive hash */ 615 u32 reserved_06[14]; 616 u32 x_cntrl; /* Transmit control register */ 617 u32 reserved_07[7]; 618 u32 paddr1; /* Physical address low */ 619 u32 paddr2; /* Physical address high + type field */ 620 u32 op_pause; /* Opcode + pause duration */ 621 u32 reserved_08[10]; 622 u32 iaddr1; /* Upper 32 bits of individual hash table */ 623 u32 iaddr2; /* Lower 32 bits of individual hash table */ 624 u32 gaddr1; /* Upper 32 bits of group hash table */ 625 u32 gaddr2; /* Lower 32 bits of group hash table */ 626 u32 reserved_09[7]; 627 u32 x_wmrk; /* Transmit FIFO watermark */ 628 u32 reserved_10; 629 u32 r_bound; /* End of RAM */ 630 u32 r_fstart; /* Receive FIFO start address */ 631 u32 reserved_11[11]; 632 u32 r_des_start; /* Beginning of receive descriptor ring */ 633 u32 x_des_start; /* Pointer to beginning of transmit descriptor ring */ 634 u32 r_buff_size; /* Receive buffer size */ 635 u32 reserved_12[26]; 636 u32 dma_control; /* DMA control for IP bus, AMBA IF + DMA revision */ 637 u32 reserved_13[2]; 638 639 u32 mib[128]; /* MIB Block Counters */ 640 641 u32 fifo[256]; /* used by FEC, can only be accessed by DMA */ 642} fec512x_t; 643 644/* 645 * ULPI 646 */ 647typedef struct ulpi512x { 648 u8 fixme[0x600]; 649} ulpi512x_t; 650 651/* 652 * UTMI 653 */ 654typedef struct utmi512x { 655 u8 fixme[0x3000]; 656} utmi512x_t; 657 658/* 659 * PCI DMA 660 */ 661typedef struct pcidma512x { 662 u8 fixme[0x300]; 663} pcidma512x_t; 664 665/* 666 * IO Control 667 */ 668typedef struct ioctrl512x { 669 u32 io_control_mem; /* MEM pad ctrl reg */ 670 u32 io_control_gp; /* GP pad ctrl reg */ 671 u32 io_control_lpc_clk; /* LPC_CLK pad ctrl reg */ 672 u32 io_control_lpc_oe; /* LPC_OE pad ctrl reg */ 673 u32 io_control_lpc_rw; /* LPC_R/W pad ctrl reg */ 674 u32 io_control_lpc_ack; /* LPC_ACK pad ctrl reg */ 675 u32 io_control_lpc_cs0; /* LPC_CS0 pad ctrl reg */ 676 u32 io_control_nfc_ce0; /* NFC_CE0 pad ctrl reg */ 677 u32 io_control_lpc_cs1; /* LPC_CS1 pad ctrl reg */ 678 u32 io_control_lpc_cs2; /* LPC_CS2 pad ctrl reg */ 679 u32 io_control_lpc_ax03; /* LPC_AX03 pad ctrl reg */ 680 u32 io_control_emb_ax02; /* EMB_AX02 pad ctrl reg */ 681 u32 io_control_emb_ax01; /* EMB_AX01 pad ctrl reg */ 682 u32 io_control_emb_ax00; /* EMB_AX00 pad ctrl reg */ 683 u32 io_control_emb_ad31; /* EMB_AD31 pad ctrl reg */ 684 u32 io_control_emb_ad30; /* EMB_AD30 pad ctrl reg */ 685 u32 io_control_emb_ad29; /* EMB_AD29 pad ctrl reg */ 686 u32 io_control_emb_ad28; /* EMB_AD28 pad ctrl reg */ 687 u32 io_control_emb_ad27; /* EMB_AD27 pad ctrl reg */ 688 u32 io_control_emb_ad26; /* EMB_AD26 pad ctrl reg */ 689 u32 io_control_emb_ad25; /* EMB_AD25 pad ctrl reg */ 690 u32 io_control_emb_ad24; /* EMB_AD24 pad ctrl reg */ 691 u32 io_control_emb_ad23; /* EMB_AD23 pad ctrl reg */ 692 u32 io_control_emb_ad22; /* EMB_AD22 pad ctrl reg */ 693 u32 io_control_emb_ad21; /* EMB_AD21 pad ctrl reg */ 694 u32 io_control_emb_ad20; /* EMB_AD20 pad ctrl reg */ 695 u32 io_control_emb_ad19; /* EMB_AD19 pad ctrl reg */ 696 u32 io_control_emb_ad18; /* EMB_AD18 pad ctrl reg */ 697 u32 io_control_emb_ad17; /* EMB_AD17 pad ctrl reg */ 698 u32 io_control_emb_ad16; /* EMB_AD16 pad ctrl reg */ 699 u32 io_control_emb_ad15; /* EMB_AD15 pad ctrl reg */ 700 u32 io_control_emb_ad14; /* EMB_AD14 pad ctrl reg */ 701 u32 io_control_emb_ad13; /* EMB_AD13 pad ctrl reg */ 702 u32 io_control_emb_ad12; /* EMB_AD12 pad ctrl reg */ 703 u32 io_control_emb_ad11; /* EMB_AD11 pad ctrl reg */ 704 u32 io_control_emb_ad10; /* EMB_AD10 pad ctrl reg */ 705 u32 io_control_emb_ad09; /* EMB_AD09 pad ctrl reg */ 706 u32 io_control_emb_ad08; /* EMB_AD08 pad ctrl reg */ 707 u32 io_control_emb_ad07; /* EMB_AD07 pad ctrl reg */ 708 u32 io_control_emb_ad06; /* EMB_AD06 pad ctrl reg */ 709 u32 io_control_emb_ad05; /* EMB_AD05 pad ctrl reg */ 710 u32 io_control_emb_ad04; /* EMB_AD04 pad ctrl reg */ 711 u32 io_control_emb_ad03; /* EMB_AD03 pad ctrl reg */ 712 u32 io_control_emb_ad02; /* EMB_AD02 pad ctrl reg */ 713 u32 io_control_emb_ad01; /* EMB_AD01 pad ctrl reg */ 714 u32 io_control_emb_ad00; /* EMB_AD00 pad ctrl reg */ 715 u32 io_control_pata_ce1; /* PATA_CE1 pad ctrl reg */ 716 u32 io_control_pata_ce2; /* PATA_CE2 pad ctrl reg */ 717 u32 io_control_pata_isolate; /* PATA_ISOLATE pad ctrl reg */ 718 u32 io_control_pata_ior; /* PATA_IOR pad ctrl reg */ 719 u32 io_control_pata_iow; /* PATA_IOW pad ctrl reg */ 720 u32 io_control_pata_iochrdy; /* PATA_IOCHRDY pad ctrl reg */ 721 u32 io_control_pata_intrq; /* PATA_INTRQ pad ctrl reg */ 722 u32 io_control_pata_drq; /* PATA_DRQ pad ctrl reg */ 723 u32 io_control_pata_dack; /* PATA_DACK pad ctrl reg */ 724 u32 io_control_nfc_wp; /* NFC_WP pad ctrl reg */ 725 u32 io_control_nfc_rb; /* NFC_RB pad ctrl reg */ 726 u32 io_control_nfc_ale; /* NFC_ALE pad ctrl reg */ 727 u32 io_control_nfc_cle; /* NFC_CLE pad ctrl reg */ 728 u32 io_control_nfc_we; /* NFC_WE pad ctrl reg */ 729 u32 io_control_nfc_re; /* NFC_RE pad ctrl reg */ 730 u32 io_control_pci_ad31; /* PCI_AD31 pad ctrl reg */ 731 u32 io_control_pci_ad30; /* PCI_AD30 pad ctrl reg */ 732 u32 io_control_pci_ad29; /* PCI_AD29 pad ctrl reg */ 733 u32 io_control_pci_ad28; /* PCI_AD28 pad ctrl reg */ 734 u32 io_control_pci_ad27; /* PCI_AD27 pad ctrl reg */ 735 u32 io_control_pci_ad26; /* PCI_AD26 pad ctrl reg */ 736 u32 io_control_pci_ad25; /* PCI_AD25 pad ctrl reg */ 737 u32 io_control_pci_ad24; /* PCI_AD24 pad ctrl reg */ 738 u32 io_control_pci_ad23; /* PCI_AD23 pad ctrl reg */ 739 u32 io_control_pci_ad22; /* PCI_AD22 pad ctrl reg */ 740 u32 io_control_pci_ad21; /* PCI_AD21 pad ctrl reg */ 741 u32 io_control_pci_ad20; /* PCI_AD20 pad ctrl reg */ 742 u32 io_control_pci_ad19; /* PCI_AD19 pad ctrl reg */ 743 u32 io_control_pci_ad18; /* PCI_AD18 pad ctrl reg */ 744 u32 io_control_pci_ad17; /* PCI_AD17 pad ctrl reg */ 745 u32 io_control_pci_ad16; /* PCI_AD16 pad ctrl reg */ 746 u32 io_control_pci_ad15; /* PCI_AD15 pad ctrl reg */ 747 u32 io_control_pci_ad14; /* PCI_AD14 pad ctrl reg */ 748 u32 io_control_pci_ad13; /* PCI_AD13 pad ctrl reg */ 749 u32 io_control_pci_ad12; /* PCI_AD12 pad ctrl reg */ 750 u32 io_control_pci_ad11; /* PCI_AD11 pad ctrl reg */ 751 u32 io_control_pci_ad10; /* PCI_AD10 pad ctrl reg */ 752 u32 io_control_pci_ad09; /* PCI_AD09 pad ctrl reg */ 753 u32 io_control_pci_ad08; /* PCI_AD08 pad ctrl reg */ 754 u32 io_control_pci_ad07; /* PCI_AD07 pad ctrl reg */ 755 u32 io_control_pci_ad06; /* PCI_AD06 pad ctrl reg */ 756 u32 io_control_pci_ad05; /* PCI_AD05 pad ctrl reg */ 757 u32 io_control_pci_ad04; /* PCI_AD04 pad ctrl reg */ 758 u32 io_control_pci_ad03; /* PCI_AD03 pad ctrl reg */ 759 u32 io_control_pci_ad02; /* PCI_AD02 pad ctrl reg */ 760 u32 io_control_pci_ad01; /* PCI_AD01 pad ctrl reg */ 761 u32 io_control_pci_ad00; /* PCI_AD00 pad ctrl reg */ 762 u32 io_control_pci_cbe0; /* PCI_CBE0 pad ctrl reg */ 763 u32 io_control_pci_cbe1; /* PCI_CBE1 pad ctrl reg */ 764 u32 io_control_pci_cbe2; /* PCI_CBE2 pad ctrl reg */ 765 u32 io_control_pci_cbe3; /* PCI_CBE3 pad ctrl reg */ 766 u32 io_control_pci_grant2; /* PCI_GRANT2 pad ctrl reg */ 767 u32 io_control_pci_req2; /* PCI_REQ2 pad ctrl reg */ 768 u32 io_control_pci_grant1; /* PCI_GRANT1 pad ctrl reg */ 769 u32 io_control_pci_req1; /* PCI_REQ1 pad ctrl reg */ 770 u32 io_control_pci_grant0; /* PCI_GRANT0 pad ctrl reg */ 771 u32 io_control_pci_req0; /* PCI_REQ0 pad ctrl reg */ 772 u32 io_control_pci_inta; /* PCI_INTA pad ctrl reg */ 773 u32 io_control_pci_clk; /* PCI_CLK pad ctrl reg */ 774 u32 io_control_pci_rst; /* PCI_RST- pad ctrl reg */ 775 u32 io_control_pci_frame; /* PCI_FRAME pad ctrl reg */ 776 u32 io_control_pci_idsel; /* PCI_IDSEL pad ctrl reg */ 777 u32 io_control_pci_devsel; /* PCI_DEVSEL pad ctrl reg */ 778 u32 io_control_pci_irdy; /* PCI_IRDY pad ctrl reg */ 779 u32 io_control_pci_trdy; /* PCI_TRDY pad ctrl reg */ 780 u32 io_control_pci_stop; /* PCI_STOP pad ctrl reg */ 781 u32 io_control_pci_par; /* PCI_PAR pad ctrl reg */ 782 u32 io_control_pci_perr; /* PCI_PERR pad ctrl reg */ 783 u32 io_control_pci_serr; /* PCI_SERR pad ctrl reg */ 784 u32 io_control_spdif_txclk; /* SPDIF_TXCLK pad ctrl reg */ 785 u32 io_control_spdif_tx; /* SPDIF_TX pad ctrl reg */ 786 u32 io_control_spdif_rx; /* SPDIF_RX pad ctrl reg */ 787 u32 io_control_i2c0_scl; /* I2C0_SCL pad ctrl reg */ 788 u32 io_control_i2c0_sda; /* I2C0_SDA pad ctrl reg */ 789 u32 io_control_i2c1_scl; /* I2C1_SCL pad ctrl reg */ 790 u32 io_control_i2c1_sda; /* I2C1_SDA pad ctrl reg */ 791 u32 io_control_i2c2_scl; /* I2C2_SCL pad ctrl reg */ 792 u32 io_control_i2c2_sda; /* I2C2_SDA pad ctrl reg */ 793 u32 io_control_irq0; /* IRQ0 pad ctrl reg */ 794 u32 io_control_irq1; /* IRQ1 pad ctrl reg */ 795 u32 io_control_can1_tx; /* CAN1_TX pad ctrl reg */ 796 u32 io_control_can2_tx; /* CAN2_TX pad ctrl reg */ 797 u32 io_control_j1850_tx; /* J1850_TX pad ctrl reg */ 798 u32 io_control_j1850_rx; /* J1850_RX pad ctrl reg */ 799 u32 io_control_psc_mclk_in; /* PSC_MCLK_IN pad ctrl reg */ 800 u32 io_control_psc0_0; /* PSC0_0 pad ctrl reg */ 801 u32 io_control_psc0_1; /* PSC0_1 pad ctrl reg */ 802 u32 io_control_psc0_2; /* PSC0_2 pad ctrl reg */ 803 u32 io_control_psc0_3; /* PSC0_3 pad ctrl reg */ 804 u32 io_control_psc0_4; /* PSC0_4 pad ctrl reg */ 805 u32 io_control_psc1_0; /* PSC1_0 pad ctrl reg */ 806 u32 io_control_psc1_1; /* PSC1_1 pad ctrl reg */ 807 u32 io_control_psc1_2; /* PSC1_2 pad ctrl reg */ 808 u32 io_control_psc1_3; /* PSC1_3 pad ctrl reg */ 809 u32 io_control_psc1_4; /* PSC1_4 pad ctrl reg */ 810 u32 io_control_psc2_0; /* PSC2_0 pad ctrl reg */ 811 u32 io_control_psc2_1; /* PSC2_1 pad ctrl reg */ 812 u32 io_control_psc2_2; /* PSC2_2 pad ctrl reg */ 813 u32 io_control_psc2_3; /* PSC2_3 pad ctrl reg */ 814 u32 io_control_psc2_4; /* PSC2_4 pad ctrl reg */ 815 u32 io_control_psc3_0; /* PSC3_0 pad ctrl reg */ 816 u32 io_control_psc3_1; /* PSC3_1 pad ctrl reg */ 817 u32 io_control_psc3_2; /* PSC3_2 pad ctrl reg */ 818 u32 io_control_psc3_3; /* PSC3_3 pad ctrl reg */ 819 u32 io_control_psc3_4; /* PSC3_4 pad ctrl reg */ 820 u32 io_control_psc4_0; /* PSC4_0 pad ctrl reg */ 821 u32 io_control_psc4_1; /* PSC4_1 pad ctrl reg */ 822 u32 io_control_psc4_2; /* PSC4_2 pad ctrl reg */ 823 u32 io_control_psc4_3; /* PSC4_3 pad ctrl reg */ 824 u32 io_control_psc4_4; /* PSC4_4 pad ctrl reg */ 825 u32 io_control_psc5_0; /* PSC5_0 pad ctrl reg */ 826 u32 io_control_psc5_1; /* PSC5_1 pad ctrl reg */ 827 u32 io_control_psc5_2; /* PSC5_2 pad ctrl reg */ 828 u32 io_control_psc5_3; /* PSC5_3 pad ctrl reg */ 829 u32 io_control_psc5_4; /* PSC5_4 pad ctrl reg */ 830 u32 io_control_psc6_0; /* PSC6_0 pad ctrl reg */ 831 u32 io_control_psc6_1; /* PSC6_1 pad ctrl reg */ 832 u32 io_control_psc6_2; /* PSC6_2 pad ctrl reg */ 833 u32 io_control_psc6_3; /* PSC6_3 pad ctrl reg */ 834 u32 io_control_psc6_4; /* PSC6_4 pad ctrl reg */ 835 u32 io_control_psc7_0; /* PSC7_0 pad ctrl reg */ 836 u32 io_control_psc7_1; /* PSC7_1 pad ctrl reg */ 837 u32 io_control_psc7_2; /* PSC7_2 pad ctrl reg */ 838 u32 io_control_psc7_3; /* PSC7_3 pad ctrl reg */ 839 u32 io_control_psc7_4; /* PSC7_4 pad ctrl reg */ 840 u32 io_control_psc8_0; /* PSC8_0 pad ctrl reg */ 841 u32 io_control_psc8_1; /* PSC8_1 pad ctrl reg */ 842 u32 io_control_psc8_2; /* PSC8_2 pad ctrl reg */ 843 u32 io_control_psc8_3; /* PSC8_3 pad ctrl reg */ 844 u32 io_control_psc8_4; /* PSC8_4 pad ctrl reg */ 845 u32 io_control_psc9_0; /* PSC9_0 pad ctrl reg */ 846 u32 io_control_psc9_1; /* PSC9_1 pad ctrl reg */ 847 u32 io_control_psc9_2; /* PSC9_2 pad ctrl reg */ 848 u32 io_control_psc9_3; /* PSC9_3 pad ctrl reg */ 849 u32 io_control_psc9_4; /* PSC9_4 pad ctrl reg */ 850 u32 io_control_psc10_0; /* PSC10_0 pad ctrl reg */ 851 u32 io_control_psc10_1; /* PSC10_1 pad ctrl reg */ 852 u32 io_control_psc10_2; /* PSC10_2 pad ctrl reg */ 853 u32 io_control_psc10_3; /* PSC10_3 pad ctrl reg */ 854 u32 io_control_psc10_4; /* PSC10_4 pad ctrl reg */ 855 u32 io_control_psc11_0; /* PSC11_0 pad ctrl reg */ 856 u32 io_control_psc11_1; /* PSC11_1 pad ctrl reg */ 857 u32 io_control_psc11_2; /* PSC11_2 pad ctrl reg */ 858 u32 io_control_psc11_3; /* PSC11_3 pad ctrl reg */ 859 u32 io_control_psc11_4; /* PSC11_4 pad ctrl reg */ 860 u32 io_control_ckstp_out; /* CKSTP_OUT pad ctrl reg */ 861 u32 io_control_usb_phy_drvvbus; /* USB2_DRVVBUS pad ctrl reg */ 862 u8 reserved[0x0cfc]; /* fill to 4096 bytes size */ 863} ioctrl512x_t; 864 865/* IO pin fields */ 866#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ 867#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ 868#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ 869#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ 870#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ 871#define IO_PIN_DS(v) ((v)) /* slew rate */ 872 873typedef struct iopin_t { 874 int p_offset; /* offset from IOCTL_MEM_OFFSET */ 875 int nr_pins; /* number of pins to set this way */ 876 int bit_or; /* or in the value instead of overwrite */ 877 u_long val; /* value to write or or */ 878}iopin_t; 879 880void iopin_initialize(iopin_t *,int); 881 882/* 883 * support to adjust individual parts of the IO pin setup 884 */ 885 886#define IO_PIN_OVER_EACH (1 << 0) /* for compatibility */ 887#define IO_PIN_OVER_FMUX (1 << 1) 888#define IO_PIN_OVER_HOLD (1 << 2) 889#define IO_PIN_OVER_PULL (1 << 3) 890#define IO_PIN_OVER_STRIG (1 << 4) 891#define IO_PIN_OVER_DRVSTR (1 << 5) 892 893void iopin_initialize_bits(iopin_t *, int); 894 895/* 896 * IIM 897 */ 898typedef struct iim512x { 899 u32 stat; /* IIM status register */ 900 u32 statm; /* IIM status IRQ mask */ 901 u32 err; /* IIM errors register */ 902 u32 emask; /* IIM error IRQ mask */ 903 u32 fctl; /* IIM fuse control register */ 904 u32 ua; /* IIM upper address register */ 905 u32 la; /* IIM lower address register */ 906 u32 sdat; /* IIM explicit sense data */ 907 u8 res0[0x08]; 908 u32 prg_p; /* IIM program protection register */ 909 u8 res1[0x10]; 910 u32 divide; /* IIM divide factor register */ 911 u8 res2[0x7c0]; 912 u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */ 913 u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */ 914 u8 res3[0x380]; 915 u32 fbac1; /* IIM fuse bank 1 protection */ 916 u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */ 917 u8 res4[0x380]; 918} iim512x_t; 919 920/* 921 * LPC 922 */ 923typedef struct lpc512x { 924 u32 cs_cfg[8]; /* Chip Select N Configuration Registers 925 No dedicated entry for CS Boot as == CS0 */ 926 u32 cs_cr; /* Chip Select Control Register */ 927 u32 cs_sr; /* Chip Select Status Register */ 928 u32 cs_bcr; /* Chip Select Burst Control Register */ 929 u32 cs_dccr; /* Chip Select Deadcycle Control Register */ 930 u32 cs_hccr; /* Chip Select Holdcycle Control Register */ 931 u32 altr; /* Address Latch Timing Register */ 932 u8 res0[0xc8]; 933 u32 sclpc_psr; /* SCLPC Packet Size Register */ 934 u32 sclpc_sar; /* SCLPC Start Address Register */ 935 u32 sclpc_cr; /* SCLPC Control Register */ 936 u32 sclpc_er; /* SCLPC Enable Register */ 937 u32 sclpc_nar; /* SCLPC NextAddress Register */ 938 u32 sclpc_sr; /* SCLPC Status Register */ 939 u32 sclpc_bdr; /* SCLPC Bytes Done Register */ 940 u32 emb_scr; /* EMB Share Counter Register */ 941 u32 emb_pcr; /* EMB Pause Control Register */ 942 u8 res1[0x1c]; 943 u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */ 944 u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */ 945 u32 lpc_cr; /* LPC RX/TX FIFO Control Register */ 946 u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */ 947 u8 res2[0xb0]; 948} lpc512x_t; 949 950/* 951 * PATA 952 */ 953typedef struct pata512x { 954 /* LOCAL Registers */ 955 u32 pata_time1; /* Time register 1: PIO and tx timing parameter */ 956 u32 pata_time2; /* Time register 2: PIO timing parameter */ 957 u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */ 958 u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */ 959 u32 pata_time5; /* Time register 5: UDMA timing parameter */ 960 u32 pata_time6; /* Time register 6: UDMA timing parameter */ 961 u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */ 962 u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */ 963 u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/ 964 u32 pata_ata_control; /* ATA Interface control register */ 965 u32 pata_irq_pending; /* Interrupt pending register (READONLY) */ 966 u32 pata_irq_enable; /* Interrupt enable register */ 967 u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/ 968 u32 pata_fifo_alarm; /* fifo alarm threshold */ 969 u32 res1[0x1A]; 970 /* DRIVE Registers */ 971 u32 pata_drive_data; /* drive data register*/ 972 u32 pata_drive_features;/* drive features register */ 973 u32 pata_drive_sectcnt; /* drive sector count register */ 974 u32 pata_drive_sectnum; /* drive sector number register */ 975 u32 pata_drive_cyllow; /* drive cylinder low register */ 976 u32 pata_drive_cylhigh; /* drive cylinder high register */ 977 u32 pata_drive_dev_head;/* drive device head register */ 978 u32 pata_drive_command; /* write = drive command, read = drive status reg */ 979 u32 res2[0x06]; 980 u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */ 981 u32 res3[0x09]; 982} pata512x_t; 983 984/* 985 * PSC 986 */ 987typedef struct psc512x { 988 volatile u8 mode; /* PSC + 0x00 */ 989 volatile u8 res0[3]; 990 union { /* PSC + 0x04 */ 991 volatile u16 status; 992 volatile u16 clock_select; 993 } sr_csr; 994#define psc_status sr_csr.status 995#define psc_clock_select sr_csr.clock_select 996 volatile u16 res1; 997 volatile u8 command; /* PSC + 0x08 */ 998 volatile u8 res2[3]; 999 union { /* PSC + 0x0c */ 1000 volatile u8 buffer_8;
1001 volatile u16 buffer_16; 1002 volatile u32 buffer_32; 1003 } buffer; 1004#define psc_buffer_8 buffer.buffer_8 1005#define psc_buffer_16 buffer.buffer_16 1006#define psc_buffer_32 buffer.buffer_32 1007 union { /* PSC + 0x10 */ 1008 volatile u8 ipcr; 1009 volatile u8 acr; 1010 } ipcr_acr; 1011#define psc_ipcr ipcr_acr.ipcr 1012#define psc_acr ipcr_acr.acr 1013 volatile u8 res3[3]; 1014 union { /* PSC + 0x14 */ 1015 volatile u16 isr; 1016 volatile u16 imr; 1017 } isr_imr; 1018#define psc_isr isr_imr.isr 1019#define psc_imr isr_imr.imr 1020 volatile u16 res4; 1021 volatile u8 ctur; /* PSC + 0x18 */ 1022 volatile u8 res5[3]; 1023 volatile u8 ctlr; /* PSC + 0x1c */ 1024 volatile u8 res6[3]; 1025 volatile u32 ccr; /* PSC + 0x20 */ 1026 volatile u8 res7[12]; 1027 volatile u8 ivr; /* PSC + 0x30 */ 1028 volatile u8 res8[3]; 1029 volatile u8 ip; /* PSC + 0x34 */ 1030 volatile u8 res9[3]; 1031 volatile u8 op1; /* PSC + 0x38 */ 1032 volatile u8 res10[3]; 1033 volatile u8 op0; /* PSC + 0x3c */ 1034 volatile u8 res11[3]; 1035 volatile u32 sicr; /* PSC + 0x40 */ 1036 volatile u8 res12[60]; 1037 volatile u32 tfcmd; /* PSC + 0x80 */ 1038 volatile u32 tfalarm; /* PSC + 0x84 */ 1039 volatile u32 tfstat; /* PSC + 0x88 */ 1040 volatile u32 tfintstat; /* PSC + 0x8C */ 1041 volatile u32 tfintmask; /* PSC + 0x90 */ 1042 volatile u32 tfcount; /* PSC + 0x94 */ 1043 volatile u16 tfwptr; /* PSC + 0x98 */ 1044 volatile u16 tfrptr; /* PSC + 0x9A */ 1045 volatile u32 tfsize; /* PSC + 0x9C */ 1046 volatile u8 res13[28]; 1047 union { /* PSC + 0xBC */ 1048 volatile u8 buffer_8; 1049 volatile u16 buffer_16; 1050 volatile u32 buffer_32; 1051 } tfdata_buffer; 1052#define tfdata_8 tfdata_buffer.buffer_8 1053#define tfdata_16 tfdata_buffer.buffer_16 1054#define tfdata_32 tfdata_buffer.buffer_32 1055 1056 volatile u32 rfcmd; /* PSC + 0xC0 */ 1057 volatile u32 rfalarm; /* PSC + 0xC4 */ 1058 volatile u32 rfstat; /* PSC + 0xC8 */ 1059 volatile u32 rfintstat; /* PSC + 0xCC */ 1060 volatile u32 rfintmask; /* PSC + 0xD0 */ 1061 volatile u32 rfcount; /* PSC + 0xD4 */ 1062 volatile u16 rfwptr; /* PSC + 0xD8 */ 1063 volatile u16 rfrptr; /* PSC + 0xDA */ 1064 volatile u32 rfsize; /* PSC + 0xDC */ 1065 volatile u8 res18[28]; 1066 union { /* PSC + 0xFC */ 1067 volatile u8 buffer_8; 1068 volatile u16 buffer_16; 1069 volatile u32 buffer_32; 1070 } rfdata_buffer; 1071#define rfdata_8 rfdata_buffer.buffer_8 1072#define rfdata_16 rfdata_buffer.buffer_16 1073#define rfdata_32 rfdata_buffer.buffer_32 1074} psc512x_t; 1075 1076/* PSC FIFO Command values */ 1077#define PSC_FIFO_RESET_SLICE 0x80 1078#define PSC_FIFO_ENABLE_SLICE 0x01 1079 1080/* PSC FIFO Controller Command values */ 1081#define FIFOC_ENABLE_CLOCK_GATE 0x01 1082#define FIFOC_DISABLE_CLOCK_GATE 0x00 1083 1084/* PSC FIFO status */ 1085#define PSC_FIFO_EMPTY 0x01 1086 1087/* PSC Command values */ 1088#define PSC_RX_ENABLE 0x01 1089#define PSC_RX_DISABLE 0x02 1090#define PSC_TX_ENABLE 0x04 1091#define PSC_TX_DISABLE 0x08 1092#define PSC_SEL_MODE_REG_1 0x10 1093#define PSC_RST_RX 0x20 1094#define PSC_RST_TX 0x30 1095#define PSC_RST_ERR_STAT 0x40 1096#define PSC_RST_BRK_CHG_INT 0x50 1097#define PSC_START_BRK 0x60 1098#define PSC_STOP_BRK 0x70 1099 1100/* PSC status register bits */ 1101#define PSC_SR_CDE 0x0080 1102#define PSC_SR_TXEMP 0x0800 1103#define PSC_SR_OE 0x1000 1104#define PSC_SR_PE 0x2000 1105#define PSC_SR_FE 0x4000 1106#define PSC_SR_RB 0x8000 1107 1108/* PSC mode fields */ 1109#define PSC_MODE_5_BITS 0x00 1110#define PSC_MODE_6_BITS 0x01 1111#define PSC_MODE_7_BITS 0x02 1112#define PSC_MODE_8_BITS 0x03 1113#define PSC_MODE_PAREVEN 0x00 1114#define PSC_MODE_PARODD 0x04 1115#define PSC_MODE_PARFORCE 0x08 1116#define PSC_MODE_PARNONE 0x10 1117#define PSC_MODE_ENTIMEOUT 0x20 1118#define PSC_MODE_RXRTS 0x80 1119#define PSC_MODE_1_STOPBIT 0x07 1120 1121/* 1122 * FIFOC 1123 */ 1124typedef struct fifoc512x { 1125 u32 fifoc_cmd; 1126 u32 fifoc_int; 1127 u32 fifoc_dma; 1128 u32 fifoc_axe; 1129 u32 fifoc_debug; 1130 u8 fixme[0xEC]; 1131} fifoc512x_t; 1132 1133/* 1134 * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs 1135 * 1136 * NOTE: individual PSC units are free to use whatever area (and size) of the 1137 * FIFOC internal memory, so make sure memory areas for FIFO slices used by 1138 * different PSCs do not overlap! 1139 * 1140 * Overall size of FIFOC memory is not documented in the MPC5121e RM, but 1141 * tests indicate that it is 1024 words total. 1142 * 1143 * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice. 1144 */ 1145#define FIFOC_PSC0_TX_SIZE 0x04 1146#define FIFOC_PSC0_TX_ADDR 0x0 1147#define FIFOC_PSC0_RX_SIZE 0x04 1148#define FIFOC_PSC0_RX_ADDR 0x10 1149 1150#define FIFOC_PSC1_TX_SIZE 0x04 1151#define FIFOC_PSC1_TX_ADDR 0x20 1152#define FIFOC_PSC1_RX_SIZE 0x04 1153#define FIFOC_PSC1_RX_ADDR 0x30 1154 1155#define FIFOC_PSC2_TX_SIZE 0x04 1156#define FIFOC_PSC2_TX_ADDR 0x40 1157#define FIFOC_PSC2_RX_SIZE 0x04 1158#define FIFOC_PSC2_RX_ADDR 0x50 1159 1160#define FIFOC_PSC3_TX_SIZE 0x04 1161#define FIFOC_PSC3_TX_ADDR 0x60 1162#define FIFOC_PSC3_RX_SIZE 0x04 1163#define FIFOC_PSC3_RX_ADDR 0x70 1164 1165#define FIFOC_PSC4_TX_SIZE 0x04 1166#define FIFOC_PSC4_TX_ADDR 0x80 1167#define FIFOC_PSC4_RX_SIZE 0x04 1168#define FIFOC_PSC4_RX_ADDR 0x90 1169 1170#define FIFOC_PSC5_TX_SIZE 0x04 1171#define FIFOC_PSC5_TX_ADDR 0xa0 1172#define FIFOC_PSC5_RX_SIZE 0x04 1173#define FIFOC_PSC5_RX_ADDR 0xb0 1174 1175#define FIFOC_PSC6_TX_SIZE 0x04 1176#define FIFOC_PSC6_TX_ADDR 0xc0 1177#define FIFOC_PSC6_RX_SIZE 0x04 1178#define FIFOC_PSC6_RX_ADDR 0xd0 1179 1180#define FIFOC_PSC7_TX_SIZE 0x04 1181#define FIFOC_PSC7_TX_ADDR 0xe0 1182#define FIFOC_PSC7_RX_SIZE 0x04 1183#define FIFOC_PSC7_RX_ADDR 0xf0 1184 1185#define FIFOC_PSC8_TX_SIZE 0x04 1186#define FIFOC_PSC8_TX_ADDR 0x100 1187#define FIFOC_PSC8_RX_SIZE 0x04 1188#define FIFOC_PSC8_RX_ADDR 0x110 1189 1190#define FIFOC_PSC9_TX_SIZE 0x04 1191#define FIFOC_PSC9_TX_ADDR 0x120 1192#define FIFOC_PSC9_RX_SIZE 0x04 1193#define FIFOC_PSC9_RX_ADDR 0x130 1194 1195#define FIFOC_PSC10_TX_SIZE 0x04 1196#define FIFOC_PSC10_TX_ADDR 0x140 1197#define FIFOC_PSC10_RX_SIZE 0x04 1198#define FIFOC_PSC10_RX_ADDR 0x150 1199 1200#define FIFOC_PSC11_TX_SIZE 0x04 1201#define FIFOC_PSC11_TX_ADDR 0x160 1202#define FIFOC_PSC11_RX_SIZE 0x04 1203#define FIFOC_PSC11_RX_ADDR 0x170 1204 1205/* 1206 * SATA 1207 */ 1208typedef struct sata512x { 1209 u8 fixme[0x2000]; 1210} sata512x_t; 1211 1212typedef struct immap { 1213 sysconf512x_t sysconf; /* System configuration */ 1214 u8 res0[0x700]; 1215 wdt512x_t wdt; /* Watch Dog Timer (WDT) */ 1216 rtclk512x_t rtc; /* Real Time Clock Module */ 1217 gpt512x_t gpt; /* General Purpose Timer */ 1218 ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */ 1219 arbiter512x_t arbiter; /* CSB Arbiter */ 1220 reset512x_t reset; /* Reset Module */ 1221 clk512x_t clk; /* Clock Module */ 1222 pmc512x_t pmc; /* Power Management Control Module */ 1223 gpio512x_t gpio; /* General purpose I/O module */ 1224 u8 res1[0x100]; 1225 mscan512x_t mscan; /* MSCAN */ 1226 bdlc512x_t bdlc; /* BDLC */ 1227 sdhc512x_t sdhc; /* SDHC */ 1228 spdif512x_t spdif; /* SPDIF */ 1229 i2c512x_t i2c; /* I2C Controllers */ 1230 u8 res2[0x800]; 1231 axe512x_t axe; /* AXE */ 1232 diu512x_t diu; /* Display Interface Unit */ 1233 cfm512x_t cfm; /* Clock Frequency Measurement */ 1234 u8 res3[0x500]; 1235 fec512x_t fec; /* Fast Ethernet Controller */ 1236 ulpi512x_t ulpi; /* USB ULPI */ 1237 u8 res4[0xa00]; 1238 utmi512x_t utmi; /* USB UTMI */ 1239 u8 res5[0x1000]; 1240 pcidma512x_t pci_dma; /* PCI DMA */ 1241 pciconf512x_t pci_conf; /* PCI Configuration */ 1242 u8 res6[0x80]; 1243 ios512x_t ios; /* PCI Sequencer */ 1244 pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ 1245 u8 res7[0xa00]; 1246 ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ 1247 ioctrl512x_t io_ctrl; /* IO Control */ 1248 iim512x_t iim; /* IC Identification module */ 1249 u8 res8[0x4000]; 1250 lpc512x_t lpc; /* LocalPlus Controller */ 1251 pata512x_t pata; /* Parallel ATA */ 1252 u8 res9[0xd00]; 1253 psc512x_t psc[12]; /* PSCs */ 1254 u8 res10[0x300]; 1255 fifoc512x_t fifoc; /* FIFO Controller */ 1256 u8 res11[0x2000]; 1257 dma512x_t dma; /* DMA */ 1258 u8 res12[0xa800]; 1259 sata512x_t sata; /* Serial ATA */ 1260 u8 res13[0xde000]; 1261} immap_t; 1262 1263/* provide interface to get PATA base address */ 1264static inline u32 get_pata_base (void) 1265{ 1266 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 1267 return (u32)(&im->pata); 1268} 1269#endif /* __ASSEMBLY__ */ 1270 1271#define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000 1272#define CONFIG_SYS_MPC512x_USB_ADDR \ 1273 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET) 1274 1275#define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim)) 1276 1277#endif /* __IMMAP_512x__ */ 1278