1/* 2 * (C) Copyright 2001 3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/************************************************************************* 25 * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com> 26 * 27 ************************************************************************/ 28 29 30/* 31 * mpsc.h - header file for MPSC in uart mode (console driver) 32 */ 33 34#ifndef __MPSC_H__ 35#define __MPSC_H__ 36 37/* include actual Galileo defines */ 38#include "../include/mv_gen_reg.h" 39 40/* driver related defines */ 41 42int mpsc_init(int baud); 43void mpsc_sdma_init(void); 44void mpsc_init2(void); 45int galbrg_set_baudrate(int channel, int rate); 46 47int mpsc_putchar_early(char ch); 48char mpsc_getchar_debug(void); 49int mpsc_test_char_debug(void); 50 51int mpsc_test_char_sdma(void); 52 53extern int (*mpsc_putchar)(char ch); 54extern char (*mpsc_getchar)(void); 55extern int (*mpsc_test_char)(void); 56 57#define CHANNEL CONFIG_MPSC_PORT 58 59#define TX_DESC 5 60#define RX_DESC 20 61 62#define DESC_FIRST 0x00010000 63#define DESC_LAST 0x00020000 64#define DESC_OWNER_BIT 0x80000000 65 66#define TX_DEMAND 0x00800000 67#define TX_STOP 0x00010000 68#define RX_ENABLE 0x00000080 69 70#define SDMA_RX_ABORT (1 << 15) 71#define SDMA_TX_ABORT (1 << 31) 72#define MPSC_TX_ABORT (1 << 7) 73#define MPSC_RX_ABORT (1 << 23) 74#define MPSC_ENTER_HUNT (1 << 31) 75 76/* MPSC defines */ 77 78#define GALMPSC_CONNECT 0x1 79#define GALMPSC_DISCONNECT 0x0 80 81#define GALMPSC_UART 0x1 82 83#define GALMPSC_STOP_BITS_1 0x0 84#define GALMPSC_STOP_BITS_2 0x1 85#define GALMPSC_CHAR_LENGTH_8 0x3 86#define GALMPSC_CHAR_LENGTH_7 0x2 87 88#define GALMPSC_PARITY_ODD 0x0 89#define GALMPSC_PARITY_EVEN 0x2 90#define GALMPSC_PARITY_MARK 0x3 91#define GALMPSC_PARITY_SPACE 0x1 92#define GALMPSC_PARITY_NONE -1 93 94#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ 95#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ 96#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ 97#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ 98#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ 99#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ 100#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ 101 102#define GALMPSC_REG_GAP 0x1000 103 104#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ 105#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ 106#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ 107#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ 108#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ 109#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ 110#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ 111#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ 112#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ 113#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ 114#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ 115#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ 116 117#define GALSDMA_COMMAND_FIRST (1 << 16) 118#define GALSDMA_COMMAND_LAST (1 << 17) 119#define GALSDMA_COMMAND_ENABLEINT (1 << 23) 120#define GALSDMA_COMMAND_AUTO (1 << 30) 121#define GALSDMA_COMMAND_OWNER (1 << 31) 122 123#define GALSDMA_RX 0 124#define GALSDMA_TX 1 125 126/* CHANNEL2 should be CHANNEL1, according to documentation, 127 * but to work with the current GTREGS file... 128 */ 129#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ 130#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ 131#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ 132#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ 133#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ 134#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ 135#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ 136#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ 137#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ 138#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ 139#define GALSDMA_REG_DIFF 0x2000 140 141/* WRONG in gt64260R.h */ 142#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ 143#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ 144#define GALMPSC_0_INT_CAUSE 0xb804 145#define GALMPSC_0_INT_MASK 0xb884 146 147#define GALSDMA_MODE_UART 0 148#define GALSDMA_MODE_BISYNC 1 149#define GALSDMA_MODE_HDLC 2 150#define GALSDMA_MODE_TRANSPARENT 3 151 152#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ 153#define GALBRG_REG_GAP 0x0008 154#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ 155 156#endif /* __MPSC_H__ */ 157