LXR uboot/board/amcc/yosemite/yosemite.c

   1/*
   2 * (C) Copyright 2006-2007
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <asm/ppc4xx.h>
  26#include <asm/processor.h>
  27#include <asm/io.h>
  28#include <spd_sdram.h>
  29#include <libfdt.h>
  30#include <fdt_support.h>
  31
  32DECLARE_GLOBAL_DATA_PTR;
  33
  34extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips     */
  35
  36static inline u32 get_async_pci_freq(void)
  37{
  38        if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
  39                CONFIG_SYS_BCSR5_PCI66EN)
  40                return 66666666;
  41        else
  42                return 33333333;
  43}
  44
  45int board_early_init_f(void)
  46{
  47        register uint reg;
  48
  49        /*--------------------------------------------------------------------
  50         * Setup the external bus controller/chip selects
  51         *-------------------------------------------------------------------*/
  52        mtdcr(EBC0_CFGADDR, EBC0_CFG);
  53        reg = mfdcr(EBC0_CFGDATA);
  54        mtdcr(EBC0_CFGDATA, reg | 0x04000000);  /* Set ATC */
  55
  56        /*--------------------------------------------------------------------
  57         * Setup the GPIO pins
  58         *-------------------------------------------------------------------*/
  59        /*CPLD cs */
  60        /*setup Address lines for flash size 64Meg. */
  61        out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
  62        out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
  63        out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
  64
  65        /*setup emac */
  66        out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  67        out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  68        out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  69        out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  70        out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  71
  72        /*UART1 */
  73        out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  74        out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  75        out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  76
  77        /* external interrupts IRQ0...3 */
  78        out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
  79        out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
  80        out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  81
  82#ifdef CONFIG_440EP
  83        /*setup USB 2.0 */
  84        out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  85        out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  86        out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  87        out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  88        out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  89#endif
  90
  91        /*--------------------------------------------------------------------
  92         * Setup the interrupt controller polarities, triggers, etc.
  93         *-------------------------------------------------------------------*/
  94        mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  95        mtdcr(UIC0ER, 0x00000000);      /* disable all */
  96        mtdcr(UIC0CR, 0x00000009);      /* ATI & UIC1 crit are critical */
  97        mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
  98        mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
  99        mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
 100        mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 101
 102        mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 103        mtdcr(UIC1ER, 0x00000000);      /* disable all */
 104        mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
 105        mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
 106        mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
 107        mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
 108        mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 109
 110        /*--------------------------------------------------------------------
 111         * Setup other serial configuration
 112         *-------------------------------------------------------------------*/
 113        mfsdr(SDR0_PCI0, reg);
 114        mtsdr(SDR0_PCI0, 0x80000000 | reg);     /* PCI arbiter enabled */
 115        mtsdr(SDR0_PFC0, 0x00003e00);   /* Pin function */
 116        mtsdr(SDR0_PFC1, 0x00048000);   /* Pin function: UART0 has 4 pins */
 117
 118        /* Check and reconfigure the PCI sync clock if necessary */
 119        ppc4xx_pci_sync_clock_config(get_async_pci_freq());
 120
 121        /*clear tmrclk divisor */
 122        *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
 123
 124        /*enable ethernet */
 125        *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
 126
 127#ifdef CONFIG_440EP
 128        /*enable usb 1.1 fs device and remove usb 2.0 reset */
 129        *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
 130#endif
 131
 132        /*get rid of flash write protect */
 133        *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
 134
 135        return 0;
 136}
 137
 138int misc_init_r (void)
 139{
 140        uint pbcr;
 141        int size_val = 0;
 142
 143        /* Re-do sizing to get full correct info */
 144        mtdcr(EBC0_CFGADDR, PB0CR);
 145        pbcr = mfdcr(EBC0_CFGDATA);
 146        switch (gd->bd->bi_flashsize) {
 147        case 1 << 20:
 148                size_val = 0;
 149                break;
 150        case 2 << 20:
 151                size_val = 1;
 152                break;
 153        case 4 << 20:
 154                size_val = 2;
 155                break;
 156        case 8 << 20:
 157                size_val = 3;
 158                break;
 159        case 16 << 20:
 160                size_val = 4;
 161                break;
 162        case 32 << 20:
 163                size_val = 5;
 164                break;
 165        case 64 << 20:
 166                size_val = 6;
 167                break;
 168        case 128 << 20:
 169                size_val = 7;
 170                break;
 171        }
 172        pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 173        mtdcr(EBC0_CFGADDR, PB0CR);
 174        mtdcr(EBC0_CFGDATA, pbcr);
 175
 176        /* adjust flash start and offset */
 177        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 178        gd->bd->bi_flashoffset = 0;
 179
 180        /* Monitor protection ON by default */
 181        (void)flash_protect(FLAG_PROTECT_SET,
 182                            -CONFIG_SYS_MONITOR_LEN,
 183                            0xffffffff,
 184                            &flash_info[0]);
 185
 186        return 0;
 187}
 188
 189int checkboard(void)
 190{
 191        char buf[64];
 192        int i = getenv_f("serial#", buf, sizeof(buf));
 193        u8 rev;
 194        u32 clock = get_async_pci_freq();
 195
 196#ifdef CONFIG_440EP
 197        printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
 198#else
 199        printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 200#endif
 201
 202        rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
 203        printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
 204
 205        if (i > 0) {
 206                puts(", serial# ");
 207                puts(buf);
 208        }
 209        putc('\n');
 210
 211        /*
 212         * Reconfiguration of the PCI sync clock is already done,
 213         * now check again if everything is in range:
 214         */
 215        if (ppc4xx_pci_sync_clock_config(clock)) {
 216                printf("ERROR: PCI clocking incorrect (async=%d "
 217                       "sync=%ld)!\n", clock, get_PCI_freq());
 218        }
 219
 220        return (0);
 221}
 222
 223/*************************************************************************
 224 *  initdram -- doesn't use serial presence detect.
 225 *
 226 *  Assumes:    256 MB, ECC, non-registered
 227 *              PLB @ 133 MHz
 228 *
 229 ************************************************************************/
 230#define NUM_TRIES 64
 231#define NUM_READS 10
 232
 233void sdram_tr1_set(int ram_address, int* tr1_value)
 234{
 235        int i;
 236        int j, k;
 237        volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
 238        int first_good = -1, last_bad = 0x1ff;
 239
 240        unsigned long test[NUM_TRIES] = {
 241                0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 242                0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 243                0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 244                0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 245                0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 246                0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 247                0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 248                0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 249                0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 250                0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 251                0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 252                0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 253                0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 254                0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 255                0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 256                0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
 257
 258        /* go through all possible SDRAM0_TR1[RDCT] values */
 259        for (i=0; i<=0x1ff; i++) {
 260                /* set the current value for TR1 */
 261                mtsdram(SDRAM0_TR1, (0x80800800 | i));
 262
 263                /* write values */
 264                for (j=0; j<NUM_TRIES; j++) {
 265                        ram_pointer[j] = test[j];
 266
 267                        /* clear any cache at ram location */
 268                        __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 269                }
 270
 271                /* read values back */
 272                for (j=0; j<NUM_TRIES; j++) {
 273                        for (k=0; k<NUM_READS; k++) {
 274                                /* clear any cache at ram location */
 275                                __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 276
 277                                if (ram_pointer[j] != test[j])
 278                                        break;
 279                        }
 280
 281                        /* read error */
 282                        if (k != NUM_READS) {
 283                                break;
 284                        }
 285                }
 286
 287                /* we have a SDRAM0_TR1[RDCT] that is part of the window */
 288                if (j == NUM_TRIES) {
 289                        if (first_good == -1)
 290                                first_good = i;         /* found beginning of window */
 291                } else { /* bad read */
 292                        /* if we have not had a good read then don't care */
 293                        if(first_good != -1) {
 294                                /* first failure after a good read */
 295                                last_bad = i-1;
 296                                break;
 297                        }
 298                }
 299        }
 300
 301        /* return the current value for TR1 */
 302        *tr1_value = (first_good + last_bad) / 2;
 303}
 304
 305phys_size_t initdram(int board)
 306{
 307        register uint reg;
 308        int tr1_bank1, tr1_bank2;
 309
 310        /*--------------------------------------------------------------------
 311         * Setup some default
 312         *------------------------------------------------------------------*/
 313        mtsdram(SDRAM0_UABBA, 0x00000000);      /* ubba=0 (default)             */
 314        mtsdram(SDRAM0_SLIO, 0x00000000);       /* rdre=0 wrre=0 rarw=0         */
 315        mtsdram(SDRAM0_DEVOPT, 0x00000000);     /* dll=0 ds=0 (normal)          */
 316        mtsdram(SDRAM0_CLKTR, 0x40000000);      /* ?? */
 317        mtsdram(SDRAM0_WDDCTR, 0x40000000);     /* ?? */
 318
 319        /*clear this first, if the DDR is enabled by a debugger
 320          then you can not make changes. */
 321        mtsdram(SDRAM0_CFG0, 0x00000000);       /* Disable EEC */
 322
 323        /*--------------------------------------------------------------------
 324         * Setup for board-specific specific mem
 325         *------------------------------------------------------------------*/
 326        /*
 327         * Following for CAS Latency = 2.5 @ 133 MHz PLB
 328         */
 329        mtsdram(SDRAM0_B0CR, 0x000a4001);       /* SDBA=0x000 128MB, Mode 3, enabled */
 330        mtsdram(SDRAM0_B1CR, 0x080a4001);       /* SDBA=0x080 128MB, Mode 3, enabled */
 331
 332        mtsdram(SDRAM0_TR0, 0x410a4012);        /* ?? */
 333        mtsdram(SDRAM0_RTR, 0x04080000);        /* ?? */
 334        mtsdram(SDRAM0_CFG1, 0x00000000);       /* Self-refresh exit, disable PM    */
 335        mtsdram(SDRAM0_CFG0, 0x30000000);       /* Disable EEC */
 336        udelay(400);            /* Delay 200 usecs (min)            */
 337
 338        /*--------------------------------------------------------------------
 339         * Enable the controller, then wait for DCEN to complete
 340         *------------------------------------------------------------------*/
 341        mtsdram(SDRAM0_CFG0, 0x80000000);       /* Enable */
 342
 343        for (;;) {
 344                mfsdram(SDRAM0_MCSTS, reg);
 345                if (reg & 0x80000000)
 346                        break;
 347        }
 348
 349        sdram_tr1_set(0x00000000, &tr1_bank1);
 350        sdram_tr1_set(0x08000000, &tr1_bank2);
 351        mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
 352
 353        return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024);       /* return bytes */
 354}
 355
 356/*************************************************************************
 357 *  hw_watchdog_reset
 358 *
 359 *      This routine is called to reset (keep alive) the watchdog timer
 360 *
 361 ************************************************************************/
 362#if defined(CONFIG_HW_WATCHDOG)
 363void hw_watchdog_reset(void)
 364{
 365
 366}
 367#endif
 368
 369void board_reset(void)
 370{
 371        /* give reset to BCSR */
 372        *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
 373}
 374