LXR uboot/board/atmel/atngw100/atngw100.c

   1/*
   2 * Copyright (C) 2006 Atmel Corporation
   3 *
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 */
  22#include <common.h>
  23
  24#include <asm/io.h>
  25#include <asm/sdram.h>
  26#include <asm/arch/clk.h>
  27#include <asm/arch/gpio.h>
  28#include <asm/arch/hmatrix.h>
  29#include <asm/arch/mmu.h>
  30#include <asm/arch/portmux.h>
  31#include <netdev.h>
  32
  33DECLARE_GLOBAL_DATA_PTR;
  34
  35struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
  36        {
  37                .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
  38                .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
  39                .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
  40                                        | MMU_VMR_CACHE_NONE,
  41        }, {
  42                .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
  43                .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
  44                .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
  45                                        | MMU_VMR_CACHE_WRBACK,
  46        },
  47};
  48
  49static const struct sdram_config sdram_config = {
  50        .data_bits      = SDRAM_DATA_16BIT,
  51        .row_bits       = 13,
  52        .col_bits       = 9,
  53        .bank_bits      = 2,
  54        .cas            = 3,
  55        .twr            = 2,
  56        .trc            = 7,
  57        .trp            = 2,
  58        .trcd           = 2,
  59        .tras           = 5,
  60        .txsr           = 5,
  61        /* 7.81 us */
  62        .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
  63};
  64
  65int board_early_init_f(void)
  66{
  67        /* Enable SDRAM in the EBI mux */
  68        hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  69
  70        portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
  71        portmux_enable_usart1(PORTMUX_DRIVE_MIN);
  72
  73#if defined(CONFIG_MACB)
  74        portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
  75        portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
  76#endif
  77#if defined(CONFIG_MMC)
  78        portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
  79#endif
  80#if defined(CONFIG_ATMEL_SPI)
  81        portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
  82#endif
  83
  84        return 0;
  85}
  86
  87phys_size_t initdram(int board_type)
  88{
  89        unsigned long expected_size;
  90        unsigned long actual_size;
  91        void *sdram_base;
  92
  93        sdram_base = uncached(EBI_SDRAM_BASE);
  94
  95        expected_size = sdram_init(sdram_base, &sdram_config);
  96        actual_size = get_ram_size(sdram_base, expected_size);
  97
  98        if (expected_size != actual_size)
  99                printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
 100                                actual_size >> 20, expected_size >> 20);
 101
 102        return actual_size;
 103}
 104
 105int board_early_init_r(void)
 106{
 107        gd->bd->bi_phy_id[0] = 0x01;
 108        gd->bd->bi_phy_id[1] = 0x03;
 109        return 0;
 110}
 111
 112#ifdef CONFIG_CMD_NET
 113int board_eth_init(bd_t *bi)
 114{
 115        macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
 116        macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
 117        return 0;
 118}
 119#endif
 120
 121/* SPI chip select control */
 122#ifdef CONFIG_ATMEL_SPI
 123#include <spi.h>
 124
 125#define ATNGW100_DATAFLASH_CS_PIN       GPIO_PIN_PA(3)
 126
 127int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 128{
 129        return bus == 0 && cs == 0;
 130}
 131
 132void spi_cs_activate(struct spi_slave *slave)
 133{
 134        gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
 135}
 136
 137void spi_cs_deactivate(struct spi_slave *slave)
 138{
 139        gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
 140}
 141#endif /* CONFIG_ATMEL_SPI */
 142