LXR uboot/board/freescale/p1010rdb/spl

   1/*
   2 * Copyright 2011 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License as
   6 * published by the Free Software Foundation; either version 2 of
   7 * the License, or (at your option) any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 *
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 * MA 02111-1307 USA
  19 *
  20 */
  21#include <common.h>
  22#include <mpc85xx.h>
  23#include <asm/io.h>
  24#include <ns16550.h>
  25#include <nand.h>
  26#include <asm/mmu.h>
  27#include <asm/immap_85xx.h>
  28#include <asm/fsl_ddr_sdram.h>
  29#include <asm/fsl_law.h>
  30#include <asm/global_data.h>
  31
  32DECLARE_GLOBAL_DATA_PTR;
  33
  34
  35void sdram_init(void)
  36{
  37        ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
  38        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  39        u32 ddr_ratio;
  40        unsigned long ddr_freq_mhz;
  41
  42        ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
  43        ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  44        ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
  45
  46        /* mask off E bit */
  47        u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
  48
  49        __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
  50        __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
  51        __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
  52        __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
  53        __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
  54
  55        if (ddr_freq_mhz < 700) {
  56                __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
  57                __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
  58                __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
  59                __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
  60                __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
  61                __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
  62                __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
  63                __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
  64                __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
  65        } else {
  66                __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
  67                __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
  68                __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
  69                __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
  70                __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
  71                __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
  72                __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
  73                __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
  74                __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
  75        }
  76
  77        __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
  78        __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
  79        __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
  80
  81        /* P1014 and it's derivatives support max 16bit DDR width */
  82        if (svr == SVR_P1014) {
  83                __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
  84                __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
  85                /* For CS0_BNDS we divide the start and end address by 2, so we can just
  86                 * shift the entire register to achieve the desired result and the mask
  87                 * the value so we don't write reserved fields */
  88                __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
  89        }
  90
  91        asm volatile("sync;isync");
  92        udelay(500);
  93
  94        /* Let the controller go */
  95        out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
  96
  97        set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
  98}
  99
 100void board_init_f(ulong bootflag)
 101{
 102        u32 plat_ratio;
 103        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 104
 105        /* initialize selected port with appropriate baud rate */
 106        plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
 107        plat_ratio >>= 1;
 108        gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
 109
 110        NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
 111                        gd->bus_clk / 16 / CONFIG_BAUDRATE);
 112
 113        puts("\nNAND boot... ");
 114
 115        /* Initialize the DDR3 */
 116        sdram_init();
 117
 118        /* copy code to RAM and jump to it - this should not return */
 119        /* NOTE - code has to be copied out of NAND buffer before
 120         * other blocks can be read.
 121         */
 122
 123        relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
 124}
 125
 126void board_init_r(gd_t *gd, ulong dest_addr)
 127{
 128        nand_boot();
 129}
 130
 131void putc(char c)
 132{
 133        if (c == '\n')
 134                NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
 135
 136        NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
 137}
 138
 139void puts(const char *str)
 140{
 141        while (*str)
 142                putc(*str++);
 143}
 144