LXR uboot/board/freescale/p1022ds/spl

   1/*
   2 * Copyright 2011 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License as
   6 * published by the Free Software Foundation; either version 2 of
   7 * the License, or (at your option) any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 *
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 * MA 02111-1307 USA
  19 *
  20 */
  21
  22#include <common.h>
  23#include <ns16550.h>
  24#include <asm/io.h>
  25#include <nand.h>
  26#include <asm/fsl_law.h>
  27#include <asm/fsl_ddr_sdram.h>
  28
  29
  30/*
  31 * Fixed sdram init -- doesn't use serial presence detect.
  32 */
  33void sdram_init(void)
  34{
  35        volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
  36
  37        __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
  38        __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
  39#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
  40        __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
  41        __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
  42#endif
  43        __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
  44        __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
  45        __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
  46        __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
  47
  48        __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
  49        __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
  50        __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
  51
  52        __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
  53        __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
  54        __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
  55
  56        __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
  57        __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
  58        __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
  59        __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
  60
  61        /* Set, but do not enable the memory */
  62        __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
  63                        &ddr->sdram_cfg);
  64
  65        in_be32(&ddr->sdram_cfg);
  66        udelay(500);
  67
  68        /* Let the controller go */
  69        out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
  70        in_be32(&ddr->sdram_cfg);
  71
  72        set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
  73}
  74
  75const static u32 sysclk_tbl[] = {
  76        66666000, 7499900, 83332500, 8999900,
  77        99999000, 11111000, 12499800, 13333200
  78};
  79
  80void board_init_f(ulong bootflag)
  81{
  82        int px_spd;
  83        u32 plat_ratio, sys_clk, bus_clk;
  84        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  85
  86        /* for FPGA */
  87        set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  88        set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  89
  90        /* initialize selected port with appropriate baud rate */
  91        px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
  92        sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
  93        plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  94        bus_clk = sys_clk * plat_ratio / 2;
  95
  96        NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  97                        bus_clk / 16 / CONFIG_BAUDRATE);
  98
  99        puts("\nNAND boot... ");
 100
 101        /* Initialize the DDR3 */
 102        sdram_init();
 103
 104        /* copy code to RAM and jump to it - this should not return */
 105        /* NOTE - code has to be copied out of NAND buffer before
 106         * other blocks can be read.
 107         */
 108        relocate_code(CONFIG_SPL_RELOC_STACK, 0,
 109                        CONFIG_SPL_RELOC_TEXT_BASE);
 110}
 111
 112void board_init_r(gd_t *gd, ulong dest_addr)
 113{
 114        nand_boot();
 115}
 116
 117void putc(char c)
 118{
 119        if (c == '\n')
 120                NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
 121
 122        NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
 123}
 124
 125void puts(const char *str)
 126{
 127        while (*str)
 128                putc(*str++);
 129}
 130