LXR uboot/board/gdsys/gdppc440etx/gdppc440etx.c

   1/*
   2 * (C) Copyright 2008
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * Based on board/amcc/yosemite/yosemite.c
   6 * (C) Copyright 2006-2007
   7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8 *
   9 * See file CREDITS for list of people who contributed to this
  10 * project.
  11 *
  12 * This program is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU General Public License as
  14 * published by the Free Software Foundation; either version 2 of
  15 * the License, or (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 * GNU General Public License for more details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 * MA 02111-1307 USA
  26 */
  27
  28#include <common.h>
  29#include <asm/ppc4xx.h>
  30#include <asm/processor.h>
  31#include <asm/io.h>
  32#include <asm/4xx_pci.h>
  33
  34DECLARE_GLOBAL_DATA_PTR;
  35
  36/* info for FLASH chips */
  37extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  38
  39int board_early_init_f(void)
  40{
  41        register uint reg;
  42
  43        /*
  44         * Setup the external bus controller/chip selects
  45         */
  46        mfebc(EBC0_CFG, reg);
  47        mtebc(EBC0_CFG, reg | 0x04000000);              /* Set ATC */
  48
  49        /*
  50         * Setup the GPIO pins
  51         */
  52
  53        /* setup Address lines for flash size 64Meg. */
  54        out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
  55        out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
  56        out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
  57
  58        /* setup emac */
  59        out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  60        out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  61        out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  62        out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  63        out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  64
  65        /* UART0 and UART1*/
  66        out32(GPIO1_TCR, in32(GPIO1_TCR)     | 0x16000000);
  67        out32(GPIO1_OSRL, in32(GPIO1_OSRL)   | 0x02180000);
  68        out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
  69        out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
  70
  71        /* disable boot-eeprom WP */
  72        out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
  73        out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
  74        out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
  75        out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
  76        out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
  77
  78        /* external interrupts IRQ0...3 */
  79        out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
  80        out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
  81        out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  82
  83
  84        /*
  85         * Setup the interrupt controller polarities, triggers, etc.
  86         */
  87        mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  88        mtdcr(UIC0ER, 0x00000000);      /* disable all */
  89        mtdcr(UIC0CR, 0x00000009);      /* ATI & UIC1 crit are critical */
  90        mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
  91        mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
  92        mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
  93        mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  94
  95        mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  96        mtdcr(UIC1ER, 0x00000000);      /* disable all */
  97        mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  98        mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
  99        mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
 100        mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
 101        mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 102
 103        /*
 104         * Setup other serial configuration
 105         */
 106        mfsdr(SDR0_PCI0, reg);
 107        mtsdr(SDR0_PCI0, 0x80000000 | reg);     /* PCI arbiter enabled */
 108        mtsdr(SDR0_PFC0, 0x00003e00);   /* Pin function */
 109        mtsdr(SDR0_PFC1, 0x00048000);   /* Pin function: UART0 has 4 pins */
 110
 111        return 0;
 112}
 113
 114int misc_init_r(void)
 115{
 116        uint pbcr;
 117        int size_val;
 118        uint sz;
 119
 120        /* Re-do sizing to get full correct info */
 121        mfebc(PB0CR, pbcr);
 122
 123        if (gd->bd->bi_flashsize > 0x08000000)
 124                panic("Max. flash banksize is 128 MB!\n");
 125
 126        for (sz = gd->bd->bi_flashsize, size_val = 7;
 127            ((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
 128                sz <<= 1;
 129
 130        pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 131        mtebc(PB0CR, pbcr);
 132
 133        /* adjust flash start and offset */
 134        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 135        gd->bd->bi_flashoffset = 0;
 136
 137        /* Monitor protection ON by default */
 138        (void)flash_protect(FLAG_PROTECT_SET,
 139                            -CONFIG_SYS_MONITOR_LEN,
 140                            0xffffffff,
 141                            &flash_info[0]);
 142
 143        return 0;
 144}
 145
 146int checkboard(void)
 147{
 148        char buf[64];
 149        int i = getenv_f("serial#", buf, sizeof(buf));
 150
 151        printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
 152
 153        if (i > 0) {
 154                puts(", serial# ");
 155                puts(buf);
 156        }
 157        putc('\n');
 158
 159        return 0;
 160}
 161
 162/*
 163 * Override weak pci_pre_init()
 164 */
 165#if defined(CONFIG_PCI)
 166int pci_pre_init(struct pci_controller *hose)
 167{
 168        /* First call common code */
 169        __pci_pre_init(hose);
 170
 171        /* enable 66 MHz ext. Clock */
 172        out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
 173        out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
 174
 175        return 1;
 176}
 177#endif  /* defined(CONFIG_PCI) */
 178