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27#include <common.h>
28#include <mpc824x.h>
29#include <pci.h>
30#include <netdev.h>
31
32int checkboard (void)
33{
34
35
36 puts ( "Board: Hidden Dragon "
37#ifdef CONFIG_MPC8240
38 "8240"
39#endif
40#ifdef CONFIG_MPC8245
41 "8245"
42#endif
43 " ##Test not implemented yet##\n");
44
45 return 0;
46}
47
48phys_size_t initdram (int board_type)
49{
50 long size;
51 long new_bank0_end;
52 long mear1;
53 long emear1;
54
55 size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
56
57 new_bank0_end = size - 1;
58 mear1 = mpc824x_mpc107_getreg(MEAR1);
59 emear1 = mpc824x_mpc107_getreg(EMEAR1);
60 mear1 = (mear1 & 0xFFFFFF00) |
61 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
62 emear1 = (emear1 & 0xFFFFFF00) |
63 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
64 mpc824x_mpc107_setreg(MEAR1, mear1);
65 mpc824x_mpc107_setreg(EMEAR1, emear1);
66
67 return (size);
68}
69
70
71
72
73#ifndef CONFIG_PCI_PNP
74static struct pci_config_table pci_hidden_dragon_config_table[] = {
75 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
76 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
77 PCI_ENET0_MEMADDR,
78 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
79 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
80 pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
81 PCI_ENET1_MEMADDR,
82 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
83 { }
84};
85#endif
86
87struct pci_controller hose = {
88#ifndef CONFIG_PCI_PNP
89 config_table: pci_hidden_dragon_config_table,
90#endif
91};
92
93void pci_init_board(void)
94{
95 pci_mpc824x_init(&hose);
96}
97
98int board_eth_init(bd_t *bis)
99{
100 return pci_eth_init(bis);
101}
102