LXR uboot/board/prodrive/p3mx/pci.c

   1/*
   2 * (C) Copyright 2000
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 *
  23 */
  24/* PCI.c - PCI functions */
  25
  26
  27#include <common.h>
  28#ifdef CONFIG_PCI
  29#include <pci.h>
  30
  31#include "../../Marvell/include/pci.h"
  32
  33#undef DEBUG
  34#undef IDE_SET_NATIVE_MODE
  35static unsigned int local_buses[] = { 0, 0 };
  36
  37static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
  38        {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
  39        {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
  40};
  41
  42#ifdef CONFIG_USE_CPCIDVI
  43typedef struct {
  44        unsigned int base;
  45        unsigned int init;
  46} GT_CPCIDVI_ROM_T;
  47
  48static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
  49#endif
  50
  51#ifdef DEBUG
  52static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
  53static void gt_pci_bus_mode_display (PCI_HOST host)
  54{
  55        unsigned int mode;
  56
  57
  58        mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
  59        switch (mode) {
  60        case 0:
  61                printf ("PCI %d bus mode: Conventional PCI\n", host);
  62                break;
  63        case 1:
  64                printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
  65                break;
  66        case 2:
  67                printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
  68                break;
  69        case 3:
  70                printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
  71                break;
  72        default:
  73                printf ("Unknown BUS %d\n", mode);
  74        }
  75}
  76#endif
  77
  78static const unsigned int pci_p2p_configuration_reg[] = {
  79        PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
  80};
  81
  82static const unsigned int pci_configuration_address[] = {
  83        PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
  84};
  85
  86static const unsigned int pci_configuration_data[] = {
  87        PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
  88        PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
  89};
  90
  91static const unsigned int pci_error_cause_reg[] = {
  92        PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
  93};
  94
  95static const unsigned int pci_arbiter_control[] = {
  96        PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
  97};
  98
  99static const unsigned int pci_address_space_en[] = {
 100        PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
 101};
 102
 103static const unsigned int pci_snoop_control_base_0_low[] = {
 104        PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
 105};
 106static const unsigned int pci_snoop_control_top_0[] = {
 107        PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
 108};
 109
 110static const unsigned int pci_access_control_base_0_low[] = {
 111        PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
 112};
 113static const unsigned int pci_access_control_top_0[] = {
 114        PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
 115};
 116
 117static const unsigned int pci_scs_bank_size[2][4] = {
 118        {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
 119         PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
 120        {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
 121         PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
 122};
 123
 124static const unsigned int pci_p2p_configuration[] = {
 125        PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
 126};
 127
 128
 129/********************************************************************
 130* pciWriteConfigReg - Write to a PCI configuration register
 131*                   - Make sure the GT is configured as a master before writing
 132*                     to another device on the PCI.
 133*                   - The function takes care of Big/Little endian conversion.
 134*
 135*
 136* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
 137*                  (or any other PCI device spec)
 138*           pciDevNum: The device number needs to be addressed.
 139*
 140*  Configuration Address 0xCF8:
 141*
 142*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 143*  |congif|Reserved|  Bus |Device|Function|Register|00|
 144*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 145*
 146*********************************************************************/
 147void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
 148                        unsigned int pciDevNum, unsigned int data)
 149{
 150        volatile unsigned int DataForAddrReg;
 151        unsigned int functionNum;
 152        unsigned int busNum = 0;
 153        unsigned int addr;
 154
 155        if (pciDevNum > 32)     /* illegal device Number */
 156                return;
 157        if (pciDevNum == SELF) {        /* configure our configuration space. */
 158                pciDevNum =
 159                        (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
 160                        0x1f;
 161                busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
 162                        0xff0000;
 163        }
 164        functionNum = regOffset & 0x00000700;
 165        pciDevNum = pciDevNum << 11;
 166        regOffset = regOffset & 0xfc;
 167        DataForAddrReg =
 168                (regOffset | pciDevNum | functionNum | busNum) | BIT31;
 169        GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
 170        GT_REG_READ (pci_configuration_address[host], &addr);
 171        if (addr != DataForAddrReg)
 172                return;
 173        GT_REG_WRITE (pci_configuration_data[host], data);
 174}
 175
 176/********************************************************************
 177* pciReadConfigReg  - Read from a PCI0 configuration register
 178*                   - Make sure the GT is configured as a master before reading
 179*                     from another device on the PCI.
 180*                   - The function takes care of Big/Little endian conversion.
 181* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
 182*                       spec)
 183*           pciDevNum: The device number needs to be addressed.
 184* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
 185*                 cause register to make sure the data is valid
 186*
 187*  Configuration Address 0xCF8:
 188*
 189*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 190*  |congif|Reserved|  Bus |Device|Function|Register|00|
 191*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 192*
 193*********************************************************************/
 194unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
 195                               unsigned int pciDevNum)
 196{
 197        volatile unsigned int DataForAddrReg;
 198        unsigned int data;
 199        unsigned int functionNum;
 200        unsigned int busNum = 0;
 201
 202        if (pciDevNum > 32)     /* illegal device Number */
 203                return 0xffffffff;
 204        if (pciDevNum == SELF) {        /* configure our configuration space. */
 205                pciDevNum =
 206                        (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
 207                        0x1f;
 208                busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
 209                        0xff0000;
 210        }
 211        functionNum = regOffset & 0x00000700;
 212        pciDevNum = pciDevNum << 11;
 213        regOffset = regOffset & 0xfc;
 214        DataForAddrReg =
 215                (regOffset | pciDevNum | functionNum | busNum) | BIT31;
 216        GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
 217        GT_REG_READ (pci_configuration_address[host], &data);
 218        if (data != DataForAddrReg)
 219                return 0xffffffff;
 220        GT_REG_READ (pci_configuration_data[host], &data);
 221        return data;
 222}
 223
 224/********************************************************************
 225* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
 226*                               the agent is placed on another Bus. For more
 227*                               information read P2P in the PCI spec.
 228*
 229* Inputs:   unsigned int regOffset - The register offset as it apears in the
 230*           GT spec (or any other PCI device spec).
 231*           unsigned int pciDevNum - The device number needs to be addressed.
 232*           unsigned int busNum - On which bus does the Target agent connect
 233*                                 to.
 234*           unsigned int data - data to be written.
 235*
 236*  Configuration Address 0xCF8:
 237*
 238*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 239*  |congif|Reserved|  Bus |Device|Function|Register|01|
 240*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 241*
 242*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
 243*   PCI spec referring to P2P.
 244*
 245*********************************************************************/
 246void pciOverBridgeWriteConfigReg (PCI_HOST host,
 247                                  unsigned int regOffset,
 248                                  unsigned int pciDevNum,
 249                                  unsigned int busNum, unsigned int data)
 250{
 251        unsigned int DataForReg;
 252        unsigned int functionNum;
 253
 254        functionNum = regOffset & 0x00000700;
 255        pciDevNum = pciDevNum << 11;
 256        regOffset = regOffset & 0xff;
 257        busNum = busNum << 16;
 258        if (pciDevNum == SELF) {        /* This board */
 259                DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
 260        } else {
 261                DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
 262                        BIT31 | BIT0;
 263        }
 264        GT_REG_WRITE (pci_configuration_address[host], DataForReg);
 265        GT_REG_WRITE (pci_configuration_data[host], data);
 266}
 267
 268
 269/********************************************************************
 270* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
 271*                               the agent target locate on another PCI bus.
 272*                             - Make sure the GT is configured as a master
 273*                               before reading from another device on the PCI.
 274*                             - The function takes care of Big/Little endian
 275*                               conversion.
 276* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
 277*                        spec). (configuration register offset.)
 278*           pciDevNum: The device number needs to be addressed.
 279*           busNum: the Bus number where the agent is place.
 280* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
 281*                 cause register to make sure the data is valid
 282*
 283*  Configuration Address 0xCF8:
 284*
 285*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 286*  |congif|Reserved|  Bus |Device|Function|Register|01|
 287*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 288*
 289*********************************************************************/
 290unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
 291                                         unsigned int regOffset,
 292                                         unsigned int pciDevNum,
 293                                         unsigned int busNum)
 294{
 295        unsigned int DataForReg;
 296        unsigned int data;
 297        unsigned int functionNum;
 298
 299        functionNum = regOffset & 0x00000700;
 300        pciDevNum = pciDevNum << 11;
 301        regOffset = regOffset & 0xff;
 302        busNum = busNum << 16;
 303        if (pciDevNum == SELF) {        /* This board */
 304                DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
 305        } else {                /* agent on another bus */
 306
 307                DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
 308                        BIT0 | BIT31;
 309        }
 310        GT_REG_WRITE (pci_configuration_address[host], DataForReg);
 311        GT_REG_READ (pci_configuration_data[host], &data);
 312        return data;
 313}
 314
 315
 316/********************************************************************
 317* pciGetRegOffset - Gets the register offset for this region config.
 318*
 319* INPUT:   Bus, Region - The bus and region we ask for its base address.
 320* OUTPUT:   N/A
 321* RETURNS: PCI register base address
 322*********************************************************************/
 323static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
 324{
 325        switch (host) {
 326        case PCI_HOST0:
 327                switch (region) {
 328                case PCI_IO:
 329                        return PCI_0I_O_LOW_DECODE_ADDRESS;
 330                case PCI_REGION0:
 331                        return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
 332                case PCI_REGION1:
 333                        return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
 334                case PCI_REGION2:
 335                        return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
 336                case PCI_REGION3:
 337                        return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
 338                }
 339        case PCI_HOST1:
 340                switch (region) {
 341                case PCI_IO:
 342                        return PCI_1I_O_LOW_DECODE_ADDRESS;
 343                case PCI_REGION0:
 344                        return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
 345                case PCI_REGION1:
 346                        return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
 347                case PCI_REGION2:
 348                        return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
 349                case PCI_REGION3:
 350                        return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
 351                }
 352        }
 353        return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
 354}
 355
 356static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
 357{
 358        switch (host) {
 359        case PCI_HOST0:
 360                switch (region) {
 361                case PCI_IO:
 362                        return PCI_0I_O_ADDRESS_REMAP;
 363                case PCI_REGION0:
 364                        return PCI_0MEMORY0_ADDRESS_REMAP;
 365                case PCI_REGION1:
 366                        return PCI_0MEMORY1_ADDRESS_REMAP;
 367                case PCI_REGION2:
 368                        return PCI_0MEMORY2_ADDRESS_REMAP;
 369                case PCI_REGION3:
 370                        return PCI_0MEMORY3_ADDRESS_REMAP;
 371                }
 372        case PCI_HOST1:
 373                switch (region) {
 374                case PCI_IO:
 375                        return PCI_1I_O_ADDRESS_REMAP;
 376                case PCI_REGION0:
 377                        return PCI_1MEMORY0_ADDRESS_REMAP;
 378                case PCI_REGION1:
 379                        return PCI_1MEMORY1_ADDRESS_REMAP;
 380                case PCI_REGION2:
 381                        return PCI_1MEMORY2_ADDRESS_REMAP;
 382                case PCI_REGION3:
 383                        return PCI_1MEMORY3_ADDRESS_REMAP;
 384                }
 385        }
 386        return PCI_0MEMORY0_ADDRESS_REMAP;
 387}
 388
 389/********************************************************************
 390* pciGetBaseAddress - Gets the base address of a PCI.
 391*           - If the PCI size is 0 then this base address has no meaning!!!
 392*
 393*
 394* INPUT:   Bus, Region - The bus and region we ask for its base address.
 395* OUTPUT:   N/A
 396* RETURNS: PCI base address.
 397*********************************************************************/
 398unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
 399{
 400        unsigned int regBase;
 401        unsigned int regEnd;
 402        unsigned int regOffset = pciGetRegOffset (host, region);
 403
 404        GT_REG_READ (regOffset, &regBase);
 405        GT_REG_READ (regOffset + 8, &regEnd);
 406
 407        if (regEnd <= regBase)
 408                return 0xffffffff;      /* ERROR !!! */
 409
 410        regBase = regBase << 16;
 411        return regBase;
 412}
 413
 414bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
 415                  unsigned int bankBase, unsigned int bankLength)
 416{
 417        unsigned int low = 0xfff;
 418        unsigned int high = 0x0;
 419        unsigned int regOffset = pciGetRegOffset (host, region);
 420        unsigned int remapOffset = pciGetRemapOffset (host, region);
 421
 422        if (bankLength != 0) {
 423                low = (bankBase >> 16) & 0xffff;
 424                high = ((bankBase + bankLength) >> 16) - 1;
 425        }
 426
 427        GT_REG_WRITE (regOffset, low | (1 << 24));      /* no swapping */
 428        GT_REG_WRITE (regOffset + 8, high);
 429
 430        if (bankLength != 0) {  /* must do AFTER writing maps */
 431                GT_REG_WRITE (remapOffset, remapBase >> 16);    /* sorry, 32 bits only.
 432                                                                   dont support upper 32
 433                                                                   in this driver */
 434        }
 435        return true;
 436}
 437
 438unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
 439{
 440        unsigned int low;
 441        unsigned int regOffset = pciGetRegOffset (host, region);
 442
 443        GT_REG_READ (regOffset, &low);
 444        return (low & 0xffff) << 16;
 445}
 446
 447unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
 448{
 449        unsigned int low, high;
 450        unsigned int regOffset = pciGetRegOffset (host, region);
 451
 452        GT_REG_READ (regOffset, &low);
 453        GT_REG_READ (regOffset + 8, &high);
 454        return ((high & 0xffff) + 1) << 16;
 455}
 456
 457
 458/* ronen - 7/Dec/03*/
 459/********************************************************************
 460* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
 461* Inputs: one of the PCI BAR
 462*********************************************************************/
 463void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
 464{
 465        RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
 466}
 467
 468void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
 469{
 470        SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
 471}
 472
 473/********************************************************************
 474* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
 475*
 476* Inputs: base and size of PCI SCS
 477*********************************************************************/
 478void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
 479                       unsigned int pciDramBase, unsigned int pciDramSize)
 480{
 481        /*ronen different function for 3rd bank. */
 482        unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
 483
 484        pciDramBase = pciDramBase & 0xfffff000;
 485        pciDramBase = pciDramBase | (pciReadConfigReg (host,
 486                                                       PCI_SCS_0_BASE_ADDRESS
 487                                                       + offset,
 488                                                       SELF) & 0x00000fff);
 489        pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
 490                           pciDramBase);
 491        if (pciDramSize == 0)
 492                pciDramSize++;
 493        GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
 494        gtPciEnableInternalBAR (host, bank);
 495}
 496
 497/********************************************************************
 498* pciSetRegionFeatures - This function modifys one of the 8 regions with
 499*                         feature bits given as an input.
 500*                       - Be advised to check the spec before modifying them.
 501* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
 502*         unsigned int features - See file: pci.h there are defintion for those
 503*                                 region features.
 504*         unsigned int baseAddress - The region base Address.
 505*         unsigned int topAddress - The region top Address.
 506* Returns: false if one of the parameters is erroneous true otherwise.
 507*********************************************************************/
 508bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
 509                           unsigned int features, unsigned int baseAddress,
 510                           unsigned int regionLength)
 511{
 512        unsigned int accessLow;
 513        unsigned int accessHigh;
 514        unsigned int accessTop = baseAddress + regionLength;
 515
 516        if (regionLength == 0) {        /* close the region. */
 517                pciDisableAccessRegion (host, region);
 518                return true;
 519        }
 520        /* base Address is store is bits [11:0] */
 521        accessLow = (baseAddress & 0xfff00000) >> 20;
 522        /* All the features are update according to the defines in pci.h (to be on
 523           the safe side we disable bits: [11:0] */
 524        accessLow = accessLow | (features & 0xfffff000);
 525        /* write to the Low Access Region register */
 526        GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
 527                      accessLow);
 528
 529        accessHigh = (accessTop & 0xfff00000) >> 20;
 530
 531        /* write to the High Access Region register */
 532        GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
 533                      accessHigh - 1);
 534        return true;
 535}
 536
 537/********************************************************************
 538* pciDisableAccessRegion - Disable The given Region by writing MAX size
 539*                           to its low Address and MIN size to its high Address.
 540*
 541* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
 542* Returns:  N/A.
 543*********************************************************************/
 544void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
 545{
 546        /* writing back the registers default values. */
 547        GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
 548                      0x01001fff);
 549        GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
 550}
 551
 552/********************************************************************
 553* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
 554*
 555* Inputs:   N/A
 556* Returns:  true.
 557*********************************************************************/
 558bool pciArbiterEnable (PCI_HOST host)
 559{
 560        unsigned int regData;
 561
 562        GT_REG_READ (pci_arbiter_control[host], &regData);
 563        GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
 564        return true;
 565}
 566
 567/********************************************************************
 568* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
 569*
 570* Inputs:   N/A
 571* Returns:  true
 572*********************************************************************/
 573bool pciArbiterDisable (PCI_HOST host)
 574{
 575        unsigned int regData;
 576
 577        GT_REG_READ (pci_arbiter_control[host], &regData);
 578        GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
 579        return true;
 580}
 581
 582/********************************************************************
 583* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
 584*
 585* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
 586*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
 587*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
 588*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
 589*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
 590*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
 591*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
 592* Returns:  true
 593*********************************************************************/
 594bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
 595                                  PCI_AGENT_PRIO externalAgent0,
 596                                  PCI_AGENT_PRIO externalAgent1,
 597                                  PCI_AGENT_PRIO externalAgent2,
 598                                  PCI_AGENT_PRIO externalAgent3,
 599                                  PCI_AGENT_PRIO externalAgent4,
 600                                  PCI_AGENT_PRIO externalAgent5)
 601{
 602        unsigned int regData;
 603        unsigned int writeData;
 604
 605        GT_REG_READ (pci_arbiter_control[host], &regData);
 606        writeData = (internalAgent << 7) + (externalAgent0 << 8) +
 607                (externalAgent1 << 9) + (externalAgent2 << 10) +
 608                (externalAgent3 << 11) + (externalAgent4 << 12) +
 609                (externalAgent5 << 13);
 610        regData = (regData & 0xffffc07f) | writeData;
 611        GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
 612        return true;
 613}
 614
 615/********************************************************************
 616* pciParkingDisable - Park on last option disable, with this function you can
 617*                      disable the park on last mechanism for each agent.
 618*                      disabling this option for all agents results parking
 619*                      on the internal master.
 620*
 621* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
 622*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
 623*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
 624*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
 625*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
 626*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
 627*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
 628* Returns:  true
 629*********************************************************************/
 630bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
 631                        PCI_AGENT_PARK externalAgent0,
 632                        PCI_AGENT_PARK externalAgent1,
 633                        PCI_AGENT_PARK externalAgent2,
 634                        PCI_AGENT_PARK externalAgent3,
 635                        PCI_AGENT_PARK externalAgent4,
 636                        PCI_AGENT_PARK externalAgent5)
 637{
 638        unsigned int regData;
 639        unsigned int writeData;
 640
 641        GT_REG_READ (pci_arbiter_control[host], &regData);
 642        writeData = (internalAgent << 14) + (externalAgent0 << 15) +
 643                (externalAgent1 << 16) + (externalAgent2 << 17) +
 644                (externalAgent3 << 18) + (externalAgent4 << 19) +
 645                (externalAgent5 << 20);
 646        regData = (regData & ~(0x7f << 14)) | writeData;
 647        GT_REG_WRITE (pci_arbiter_control[host], regData);
 648        return true;
 649}
 650
 651/********************************************************************
 652* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
 653*                       respond to grant assertion within a window specified in
 654*                       the input value: 'brokenValue'.
 655*
 656* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
 657*                       grant without asserting frame.
 658* Returns:  Error for illegal broken value otherwise true.
 659*********************************************************************/
 660bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
 661{
 662        unsigned int data;
 663        unsigned int regData;
 664
 665        if (brokenValue > 0xf)
 666                return false;   /* brokenValue must be 4 bit */
 667        data = brokenValue << 3;
 668        GT_REG_READ (pci_arbiter_control[host], &regData);
 669        regData = (regData & 0xffffff87) | data;
 670        GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
 671        return true;
 672}
 673
 674/********************************************************************
 675* pciDisableBrokenAgentDetection - This function disable the Broken agent
 676*                           Detection mechanism.
 677*                           NOTE: This operation may cause a dead lock on the
 678*                           pci0 arbitration.
 679*
 680* Inputs:   N/A
 681* Returns:  true.
 682*********************************************************************/
 683bool pciDisableBrokenAgentDetection (PCI_HOST host)
 684{
 685        unsigned int regData;
 686
 687        GT_REG_READ (pci_arbiter_control[host], &regData);
 688        regData = regData & 0xfffffffd;
 689        GT_REG_WRITE (pci_arbiter_control[host], regData);
 690        return true;
 691}
 692
 693/********************************************************************
 694* pciP2PConfig - This function set the PCI_n P2P configurate.
 695*                 For more information on the P2P read PCI spec.
 696*
 697* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
 698*                                      Boundry.
 699*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
 700*                                      Boundry.
 701*          unsigned int busNum - The CPI bus number to which the PCI interface
 702*                                      is connected.
 703*          unsigned int devNum - The PCI interface's device number.
 704*
 705* Returns:  true.
 706*********************************************************************/
 707bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
 708                   unsigned int SecondBusHigh,
 709                   unsigned int busNum, unsigned int devNum)
 710{
 711        unsigned int regData;
 712
 713        regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
 714                ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
 715        GT_REG_WRITE (pci_p2p_configuration[host], regData);
 716        return true;
 717}
 718
 719/********************************************************************
 720* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
 721*                          supports Cache Coherency in the PCI_n interface.
 722* Inputs: region - One of the four regions.
 723*         snoopType - There is four optional Types:
 724*                        1. No Snoop.
 725*                        2. Snoop to WT region.
 726*                        3. Snoop to WB region.
 727*                        4. Snoop & Invalidate to WB region.
 728*         baseAddress - Base Address of this region.
 729*         regionLength - Region length.
 730* Returns: false if one of the parameters is wrong otherwise return true.
 731*********************************************************************/
 732bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
 733                            PCI_SNOOP_TYPE snoopType,
 734                            unsigned int baseAddress,
 735                            unsigned int regionLength)
 736{
 737        unsigned int snoopXbaseAddress;
 738        unsigned int snoopXtopAddress;
 739        unsigned int data;
 740        unsigned int snoopHigh = baseAddress + regionLength;
 741
 742        if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
 743                return false;
 744        snoopXbaseAddress =
 745                pci_snoop_control_base_0_low[host] + 0x10 * region;
 746        snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
 747        if (regionLength == 0) {        /* closing the region */
 748                GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
 749                GT_REG_WRITE (snoopXtopAddress, 0);
 750                return true;
 751        }
 752        baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
 753        data = (baseAddress >> 20) | snoopType << 12;
 754        GT_REG_WRITE (snoopXbaseAddress, data);
 755        snoopHigh = (snoopHigh & 0xfff00000) >> 20;
 756        GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
 757        return true;
 758}
 759
 760static int gt_read_config_dword (struct pci_controller *hose,
 761                                 pci_dev_t dev, int offset, u32 * value)
 762{
 763        int bus = PCI_BUS (dev);
 764
 765        if ((bus == local_buses[0]) || (bus == local_buses[1])) {
 766                *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
 767                                           PCI_DEV (dev));
 768        } else {
 769                *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
 770                                                     cfg_addr, offset,
 771                                                     PCI_DEV (dev), bus);
 772        }
 773
 774        return 0;
 775}
 776
 777static int gt_write_config_dword (struct pci_controller *hose,
 778                                  pci_dev_t dev, int offset, u32 value)
 779{
 780        int bus = PCI_BUS (dev);
 781
 782        if ((bus == local_buses[0]) || (bus == local_buses[1])) {
 783                pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
 784                                   PCI_DEV (dev), value);
 785        } else {
 786                pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
 787                                             offset, PCI_DEV (dev), bus,
 788                                             value);
 789        }
 790        return 0;
 791}
 792
 793
 794static void gt_setup_ide (struct pci_controller *hose,
 795                          pci_dev_t dev, struct pci_config_table *entry)
 796{
 797        static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
 798        u32 bar_response, bar_value;
 799        int bar;
 800
 801        for (bar = 0; bar < 6; bar++) {
 802                /*ronen different function for 3rd bank. */
 803                unsigned int offset =
 804                        (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
 805
 806                pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
 807                                             0x0);
 808                pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
 809                                            &bar_response);
 810
 811                pciauto_region_allocate (bar_response &
 812                                         PCI_BASE_ADDRESS_SPACE_IO ? hose->
 813                                         pci_io : hose->pci_mem, ide_bar[bar],
 814                                         &bar_value);
 815
 816                pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
 817                                             bar_value);
 818        }
 819}
 820
 821#ifdef CONFIG_USE_CPCIDVI
 822static void gt_setup_cpcidvi (struct pci_controller *hose,
 823                              pci_dev_t dev, struct pci_config_table *entry)
 824{
 825        u32               bar_value, pci_response;
 826
 827        pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
 828        pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
 829        pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
 830        pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
 831        pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
 832        pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
 833        pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
 834        pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
 835        gt_cpcidvi_rom.base = bar_value & 0xffffff00;
 836        gt_cpcidvi_rom.init = 1;
 837}
 838
 839unsigned char gt_cpcidvi_in8(unsigned int offset)
 840{
 841        unsigned char     data;
 842
 843        if (gt_cpcidvi_rom.init == 0) {
 844                return(0);
 845                }
 846        data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
 847        return(data);
 848}
 849
 850void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
 851{
 852        unsigned int      off;
 853
 854        if (gt_cpcidvi_rom.init == 0) {
 855                return;
 856        }
 857        off = data;
 858        off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
 859        in8(off);
 860        return;
 861}
 862#endif
 863
 864/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
 865/* and is curently not called *. */
 866#if 0
 867static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 868{
 869        unsigned char pin, irq;
 870
 871        pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
 872
 873        if (pin == 1) {         /* only allow INT A */
 874                irq = pci_irq_swizzle[(PCI_HOST) hose->
 875                                      cfg_addr][PCI_DEV (dev)];
 876                if (irq)
 877                        pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
 878        }
 879}
 880#endif
 881
 882struct pci_config_table gt_config_table[] = {
 883#ifdef CONFIG_USE_CPCIDVI
 884        {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
 885         PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
 886#endif
 887        {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
 888         PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
 889        {}
 890};
 891
 892struct pci_controller pci0_hose = {
 893/*    fixup_irq: gt_fixup_irq, */
 894        config_table:gt_config_table,
 895};
 896
 897struct pci_controller pci1_hose = {
 898/*    fixup_irq: gt_fixup_irq, */
 899        config_table:gt_config_table,
 900};
 901
 902void pci_init_board (void)
 903{
 904        unsigned int command;
 905#ifdef CONFIG_PCI_PNP
 906        unsigned int bar;
 907#endif
 908#ifdef DEBUG
 909        gt_pci_bus_mode_display (PCI_HOST0);
 910#endif
 911#ifdef CONFIG_USE_CPCIDVI
 912        gt_cpcidvi_rom.init = 0;
 913        gt_cpcidvi_rom.base = 0;
 914#endif
 915
 916        pci0_hose.config_table = gt_config_table;
 917        pci1_hose.config_table = gt_config_table;
 918
 919#ifdef CONFIG_USE_CPCIDVI
 920        gt_config_table[0].config_device =  gt_setup_cpcidvi;
 921#endif
 922        gt_config_table[1].config_device =  gt_setup_ide;
 923
 924        pci0_hose.first_busno = 0;
 925        pci0_hose.last_busno = 0xff;
 926        local_buses[0] = pci0_hose.first_busno;
 927
 928        /* PCI memory space */
 929        pci_set_region (pci0_hose.regions + 0,
 930                        CONFIG_SYS_PCI0_0_MEM_SPACE,
 931                        CONFIG_SYS_PCI0_0_MEM_SPACE,
 932                        CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 933
 934        /* PCI I/O space */
 935        pci_set_region (pci0_hose.regions + 1,
 936                        CONFIG_SYS_PCI0_IO_SPACE_PCI,
 937                        CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 938
 939        pci_set_ops (&pci0_hose,
 940                     pci_hose_read_config_byte_via_dword,
 941                     pci_hose_read_config_word_via_dword,
 942                     gt_read_config_dword,
 943                     pci_hose_write_config_byte_via_dword,
 944                     pci_hose_write_config_word_via_dword,
 945                     gt_write_config_dword);
 946        pci0_hose.region_count = 2;
 947
 948        pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
 949
 950        pci_register_hose (&pci0_hose);
 951        pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */
 952        pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
 953        command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
 954        command |= PCI_COMMAND_MASTER;
 955        pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
 956        command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
 957        command |= PCI_COMMAND_MEMORY;
 958        pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
 959
 960#ifdef CONFIG_PCI_PNP
 961        pciauto_config_init(&pci0_hose);
 962        pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
 963#endif
 964#ifdef CONFIG_PCI_SCAN_SHOW
 965        printf("PCI:   Bus Dev VenId DevId Class Int\n");
 966#endif
 967        pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
 968
 969#ifdef DEBUG
 970        gt_pci_bus_mode_display (PCI_HOST1);
 971#endif
 972        pci1_hose.first_busno = pci0_hose.last_busno + 1;
 973        pci1_hose.last_busno = 0xff;
 974        pci1_hose.current_busno = pci1_hose.first_busno;
 975        local_buses[1] = pci1_hose.first_busno;
 976
 977        /* PCI memory space */
 978        pci_set_region (pci1_hose.regions + 0,
 979                        CONFIG_SYS_PCI1_0_MEM_SPACE,
 980                        CONFIG_SYS_PCI1_0_MEM_SPACE,
 981                        CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 982
 983        /* PCI I/O space */
 984        pci_set_region (pci1_hose.regions + 1,
 985                        CONFIG_SYS_PCI1_IO_SPACE_PCI,
 986                        CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 987
 988        pci_set_ops (&pci1_hose,
 989                     pci_hose_read_config_byte_via_dword,
 990                     pci_hose_read_config_word_via_dword,
 991                     gt_read_config_dword,
 992                     pci_hose_write_config_byte_via_dword,
 993                     pci_hose_write_config_word_via_dword,
 994                     gt_write_config_dword);
 995
 996        pci1_hose.region_count = 2;
 997
 998        pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
 999
1000        pci_register_hose (&pci1_hose);

1001
1002        pciArbiterEnable (PCI_HOST1);
1003        pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
1004
1005        command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
1006        command |= PCI_COMMAND_MASTER;
1007        pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
1008
1009#ifdef CONFIG_PCI_PNP
1010        pciauto_config_init(&pci1_hose);
1011        pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
1012#endif
1013        pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
1014
1015        command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
1016        command |= PCI_COMMAND_MEMORY;
1017        pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
1018
1019}
1020#endif /* of CONFIG_PCI */
1021