1/* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#include <mpc8xx_irq.h> 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_MPC860 1 38#define CONFIG_MPC860T 1 39#define CONFIG_ICU862 1 40#define CONFIG_MPC862 1 41 42#define CONFIG_SYS_TEXT_BASE 0x40F00000 43 44#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 45#undef CONFIG_8xx_CONS_SMC2 46#undef CONFIG_8xx_CONS_NONE 47#define CONFIG_BAUDRATE 9600 48#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 49 50#ifdef CONFIG_100MHz 51#define MPC8XX_FACT 24 /* Multiply by 24 */ 52#define MPC8XX_XIN 4165000 /* 4.165 MHz in */ 53#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) 54 /* define if cant' use get_gclk_freq */ 55#else 56#if 1 /* for 50MHz version of processor */ 57#define MPC8XX_FACT 12 /* Multiply by 12 */ 58#define MPC8XX_XIN 4000000 /* 4 MHz in */ 59#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */ 60#else /* for 80MHz version of processor */ 61#define MPC8XX_FACT 20 /* Multiply by 20 */ 62#define MPC8XX_XIN 4000000 /* 4 MHz in */ 63#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */ 64#endif 65#endif 66 67#if 0 68#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 69#else 70#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 71#endif 72 73#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 74 75#undef CONFIG_BOOTARGS 76#define CONFIG_BOOTCOMMAND \ 77 "bootp;" \ 78 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 79 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ 80 "bootm" 81 82#undef CONFIG_WATCHDOG /* watchdog disabled */ 83 84#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 85 86/* 87 * BOOTP options 88 */ 89#define CONFIG_BOOTP_SUBNETMASK 90#define CONFIG_BOOTP_GATEWAY 91#define CONFIG_BOOTP_HOSTNAME 92#define CONFIG_BOOTP_BOOTPATH 93#define CONFIG_BOOTP_BOOTFILESIZE 94 95 96#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ 97#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ 98#define CONFIG_MII 1 99#if 1 100#define CONFIG_SYS_DISCOVER_PHY 1 101#else 102#undef CONFIG_SYS_DISCOVER_PHY 103#endif 104 105#define CONFIG_MAC_PARTITION 106#define CONFIG_DOS_PARTITION 107 108/* enable I2C and select the hardware/software driver */ 109#undef CONFIG_HARD_I2C /* I2C with hardware support */ 110#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 111# define CONFIG_SYS_I2C_SPEED 50000 112# define CONFIG_SYS_I2C_SLAVE 0xFE 113# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 114# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 115/* 116 * Software (bit-bang) I2C driver configuration 117 */ 118#define PB_SCL 0x00000020 /* PB 26 */ 119#define PB_SDA 0x00000010 /* PB 27 */ 120 121#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 122#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 123#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 124#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 125#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 126 else immr->im_cpm.cp_pbdat &= ~PB_SDA 127#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 128 else immr->im_cpm.cp_pbdat &= ~PB_SCL 129#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 130 131#define CONFIG_SYS_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */ 132#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */ 133 134#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 135 136 137/* 138 * Command line configuration. 139 */ 140#include <config_cmd_default.h> 141 142#define CONFIG_CMD_ASKENV 143#define CONFIG_CMD_DATE 144#define CONFIG_CMD_DHCP 145#define CONFIG_CMD_EEPROM 146#define CONFIG_CMD_I2C 147#define CONFIG_CMD_IDE 148#define CONFIG_CMD_NFS 149#define CONFIG_CMD_SNTP 150 151 152/* 153 * Miscellaneous configurable options 154 */ 155#define CONFIG_SYS_LONGHELP /* undef to save memory */ 156#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 157#if defined(CONFIG_CMD_KGDB) 158#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 159#else 160#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 161#endif 162#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 163#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 164#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 165 166#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ 167#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ 168 169#define CONFIG_SYS_LOAD_ADDR 0x00100000 170 171#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 172 173/* 174 * Low Level Configuration Settings 175 * (address mappings, register initial values, etc.) 176 * You should know what you are doing if you make changes here. 177 */ 178/*----------------------------------------------------------------------- 179 * Internal Memory Mapped Register 180 */ 181#define CONFIG_SYS_IMMR 0xF0000000 182#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) 183 184/*----------------------------------------------------------------------- 185 * Definitions for initial stack pointer and data area (in DPRAM) 186 */ 187#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 188#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 189#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 190#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 191 192/*----------------------------------------------------------------------- 193 * Start addresses for the final memory configuration 194 * (Set up by the startup code) 195 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 196 */ 197#define CONFIG_SYS_SDRAM_BASE 0x00000000 198#define CONFIG_SYS_FLASH_BASE 0x40000000 199#define CONFIG_SYS_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ 200 201#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 202 203#if 0 204#if defined(DEBUG) 205#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 206#else 207#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 208#endif 209#else 210#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 211#endif 212#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 213#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ 214 215/* 216 * For booting Linux, the board info and command line data 217 * have to be in the first 8 MB of memory, since this is 218 * the maximum mapped by the Linux kernel during initialization. 219 */ 220#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 221/*----------------------------------------------------------------------- 222 * FLASH organization 223 */ 224#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 225#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ 226 227#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 228#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 229 230 231#define CONFIG_ENV_IS_IN_FLASH 1 232#define CONFIG_ENV_OFFSET 0x00F40000 233 234#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ 235#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ 236#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 237 238/*----------------------------------------------------------------------- 239 * Cache Configuration 240 */ 241#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 242#if defined(CONFIG_CMD_KGDB) 243#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 244#endif 245 246/*----------------------------------------------------------------------- 247 * SYPCR - System Protection Control 11-9 248 * SYPCR can only be written once after reset! 249 *----------------------------------------------------------------------- 250 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 251 */ 252#if defined(CONFIG_WATCHDOG) 253#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 254 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 255#else 256#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 257#endif 258 259/*----------------------------------------------------------------------- 260 * SIUMCR - SIU Module Configuration 11-6 261 *----------------------------------------------------------------------- 262 * PCMCIA config., multi-function pin tri-state 263 */ 264#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 265 266/*----------------------------------------------------------------------- 267 * TBSCR - Time Base Status and Control 11-26 268 *----------------------------------------------------------------------- 269 * Clear Reference Interrupt Status, Timebase freezing enabled 270 */ 271#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) 272 273/*----------------------------------------------------------------------- 274 * PISCR - Periodic Interrupt Status and Control 11-31 275 *----------------------------------------------------------------------- 276 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 277 */ 278#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 279 280/*----------------------------------------------------------------------- 281 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 282 *----------------------------------------------------------------------- 283 * set the PLL, the low-power modes and the reset control (15-29) 284 */ 285#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ 286 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 287 288/*----------------------------------------------------------------------- 289 * SCCR - System Clock and reset Control Register 15-27 290 *----------------------------------------------------------------------- 291 * Set clock output, timebase and RTC source and divider, 292 * power management and some other internal clocks 293 */ 294#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */ 295#define SCCR_MASK 0 296#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ 297 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ 298 SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01) 299#else /* up to 50 MHz we use a 1:1 clock */ 300#define SCCR_MASK SCCR_EBDF11 301#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ 302 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ 303 SCCR_DFLCD000 |SCCR_DFALCD00 ) 304#endif /* CONFIG_100MHz */ 305 306/*----------------------------------------------------------------------- 307 * RCCR - RISC Controller Configuration Register 19-4 308 *----------------------------------------------------------------------- 309 */ 310/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ 311#define CONFIG_SYS_RCCR 0x0020 312 313/*----------------------------------------------------------------------- 314 * PCMCIA stuff 315 *----------------------------------------------------------------------- 316 */ 317#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 318#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 319#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 320#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 321#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 322#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 323#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 324#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 325 326/*----------------------------------------------------------------------- 327 * PCMCIA Power Switch 328 * 329 * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to 330 * control the voltages on the PCMCIA slot which is connected to Port B 331 *----------------------------------------------------------------------- 332 */ 333 /* Output pins */ 334#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */ 335#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */ 336#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */ 337#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */ 338#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */ 339#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \ 340 TPS2205_VPP_PGM | TPS2205_VPP_VCC | \ 341 TPS2205_SHDN) 342 343 /* Input pins */ 344#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */ 345#define TPS2205_INPUTS ( TPS2205_OC ) 346 347/*----------------------------------------------------------------------- 348 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 349 *----------------------------------------------------------------------- 350 */ 351 352#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 353#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 354 355#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 356#undef CONFIG_IDE_LED /* LED for ide not supported */ 357#undef CONFIG_IDE_RESET /* reset for ide not supported */ 358 359#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 360#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 361 362#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 363 364#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 365 366/* Offset for data I/O */ 367#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 368 369/* Offset for normal register accesses */ 370#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 371 372/* Offset for alternate registers */ 373#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 374 375 376 /*----------------------------------------------------------------------- 377 * 378 *----------------------------------------------------------------------- 379 * 380 */ 381#define CONFIG_SYS_DER 0 382 383/* Because of the way the 860 starts up and assigns CS0 the 384* entire address space, we have to set the memory controller 385* differently. Normally, you write the option register 386* first, and then enable the chip select by writing the 387* base register. For CS0, you must write the base register 388* first, followed by the option register. 389*/ 390 391/* 392 * Init Memory Controller: 393 * 394 * BR0 and OR0 (FLASH) 395 */ 396 397#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 398#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */ 399 400#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 401#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 402 403/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ 404#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) 405 406#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 407 408#define CONFIG_SYS_OR0_PRELIM 0xFF000954 /* Real values for the board */ 409#define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */ 410 411/* 412 * BR1 and OR1 (SDRAM) 413 */ 414#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */ 415#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 416 417#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */ 418 419#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) 420#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) 421 422/* 423 * Memory Periodic Timer Prescaler 424 */ 425 426/* periodic timer for refresh */ 427#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ 428 429/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 430#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 431#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 432 433/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 434#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 435#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 436 437/* 438 * MAMR settings for SDRAM 439 */ 440 441/* 8 column SDRAM */ 442#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 443 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 444 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 445/* 9 column SDRAM */ 446#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 447 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 448 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 449 450#define CONFIG_SYS_MAMR 0x13a01114 451 452#ifdef CONFIG_MPC860T 453 454/* Interrupt level assignments. 455*/ 456#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ 457 458#endif /* CONFIG_MPC860T */ 459 460 461#endif /* __CONFIG_H */ 462