1/* 2 * (C) Copyright 2000, 2001, 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 37#define CONFIG_RRVISION 1 /* ...on a RRvision board */ 38 39#define CONFIG_SYS_TEXT_BASE 0x40000000 40 41#define CONFIG_8xx_GCLK_FREQ 64000000 42 43#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 44#undef CONFIG_8xx_CONS_SMC2 45#undef CONFIG_8xx_CONS_NONE 46#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 47#if 0 48#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 49#else 50#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ 51#endif 52 53#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 54 55#define CONFIG_PREBOOT "setenv stdout serial" 56 57#undef CONFIG_BOOTARGS 58#define CONFIG_ETHADDR 00:50:C2:00:E0:70 59#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 60#define CONFIG_IPADDR 10.0.0.5 61#define CONFIG_SERVERIP 10.0.0.2 62#define CONFIG_NETMASK 255.0.0.0 63#define CONFIG_ROOTPATH "/opt/eldk/ppc_8xx" 64#define CONFIG_BOOTCOMMAND "run flash_self" 65 66#define CONFIG_EXTRA_ENV_SETTINGS \ 67 "netdev=eth0\0" \ 68 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 69 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 70 "nfsroot=${serverip}:${rootpath}\0" \ 71 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \ 72 ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ 73 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 74 "load=tftp 100000 /tftpboot/u-boot.bin\0" \ 75 "update=protect off 1:0-8;era 1:0-8;" \ 76 "cp.b 100000 40000000 ${filesize};" \ 77 "setenv filesize;saveenv\0" \ 78 "kernel_addr=40040000\0" \ 79 "ramdisk_addr=40100000\0" \ 80 "kernel_img=/tftpboot/uImage\0" \ 81 "kernel_load=tftp 200000 ${kernel_img}\0" \ 82 "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \ 83 "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \ 84 "flash_self=run ramargs addip addtty;" \ 85 "bootm ${kernel_addr} ${ramdisk_addr}\0" 86 87 88#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 89#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 90 91#undef CONFIG_WATCHDOG /* watchdog disabled */ 92 93#undef CONFIG_STATUS_LED /* disturbs display */ 94 95#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 96 97/* 98 * BOOTP options 99 */ 100#define CONFIG_BOOTP_SUBNETMASK 101#define CONFIG_BOOTP_GATEWAY 102#define CONFIG_BOOTP_HOSTNAME 103#define CONFIG_BOOTP_BOOTPATH 104#define CONFIG_BOOTP_BOOTFILESIZE 105 106 107#define CONFIG_MAC_PARTITION 108#define CONFIG_DOS_PARTITION 109 110#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 111 112 113#ifdef CONFIG_LCD 114#define CONFIG_MPC8XX_LCD 115#else 116#define CONFIG_VIDEO 1 /* To enable the video initialization */ 117 118/* Video related */ 119#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ 120#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */ 121#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */ 122#endif 123 124/* enable I2C and select the hardware/software driver */ 125#undef CONFIG_HARD_I2C /* I2C with hardware support */ 126#define CONFIG_SOFT_I2C /* I2C bit-banged */ 127 128# define CONFIG_SYS_I2C_SPEED 50000 /* 50 kHz is supposed to work */ 129# define CONFIG_SYS_I2C_SLAVE 0xFE 130 131#ifdef CONFIG_SOFT_I2C 132/* 133 * Software (bit-bang) I2C driver configuration 134 */ 135#define PB_SCL 0x00000020 /* PB 26 */ 136#define PB_SDA 0x00000010 /* PB 27 */ 137 138#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 139#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 140#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 141#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 142#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 143 else immr->im_cpm.cp_pbdat &= ~PB_SDA 144#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 145 else immr->im_cpm.cp_pbdat &= ~PB_SCL 146#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */ 147#endif /* CONFIG_SOFT_I2C */ 148 149 150/* 151 * Command line configuration. 152 */ 153#include <config_cmd_default.h> 154 155#define CONFIG_CMD_DHCP 156#define CONFIG_CMD_I2C 157#define CONFIG_CMD_IDE 158#define CONFIG_CMD_DATE 159 160#undef CONFIG_CMD_PCMCIA 161#undef CONFIG_CMD_IDE 162 163 164/* 165 * Miscellaneous configurable options 166 */ 167#define CONFIG_SYS_LONGHELP /* undef to save memory */ 168#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 169#if defined(CONFIG_CMD_KGDB) 170#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 171#else 172#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 173#endif 174#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 175#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 176#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 177 178#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 179#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 180 181#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 182 183#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 184 185/* 186 * Low Level Configuration Settings 187 * (address mappings, register initial values, etc.) 188 * You should know what you are doing if you make changes here. 189 */ 190/*----------------------------------------------------------------------- 191 * Internal Memory Mapped Register 192 */ 193#define CONFIG_SYS_IMMR 0xFFF00000 194 195/*----------------------------------------------------------------------- 196 * Definitions for initial stack pointer and data area (in DPRAM) 197 */ 198#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 199#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 200#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 201#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 202 203/*----------------------------------------------------------------------- 204 * Start addresses for the final memory configuration 205 * (Set up by the startup code) 206 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 207 */ 208#define CONFIG_SYS_SDRAM_BASE 0x00000000 209#define CONFIG_SYS_FLASH_BASE 0x40000000 210#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 211#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 212#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 213 214/* 215 * For booting Linux, the board info and command line data 216 * have to be in the first 8 MB of memory, since this is 217 * the maximum mapped by the Linux kernel during initialization. 218 */ 219#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 220 221/*----------------------------------------------------------------------- 222 * FLASH organization 223 */ 224#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 225#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 226 227/* timeout values are in ticks = ms */ 228#define CONFIG_SYS_FLASH_ERASE_TOUT (120*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 229#define CONFIG_SYS_FLASH_WRITE_TOUT (1 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 230 231#define CONFIG_ENV_IS_IN_FLASH 1 232#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 233#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 234 235/* Address and size of Redundant Environment Sector */ 236#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 237#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 238 239#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 240 241/*----------------------------------------------------------------------- 242 * Cache Configuration 243 */ 244#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 245#if defined(CONFIG_CMD_KGDB) 246#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 247#endif 248 249/*----------------------------------------------------------------------- 250 * SYPCR - System Protection Control 11-9 251 * SYPCR can only be written once after reset! 252 *----------------------------------------------------------------------- 253 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 254 */ 255#if defined(CONFIG_WATCHDOG) 256#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 257 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 258#else 259#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 260#endif 261 262/*----------------------------------------------------------------------- 263 * SIUMCR - SIU Module Configuration 11-6 264 *----------------------------------------------------------------------- 265 * PCMCIA config., multi-function pin tri-state 266 */ 267#ifndef CONFIG_CAN_DRIVER 268#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 269#else /* we must activate GPL5 in the SIUMCR for CAN */ 270#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 271#endif /* CONFIG_CAN_DRIVER */ 272 273/*----------------------------------------------------------------------- 274 * TBSCR - Time Base Status and Control 11-26 275 *----------------------------------------------------------------------- 276 * Clear Reference Interrupt Status, Timebase freezing enabled 277 */ 278#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 279 280/*----------------------------------------------------------------------- 281 * RTCSC - Real-Time Clock Status and Control Register 11-27 282 *----------------------------------------------------------------------- 283 */ 284#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 285 286/*----------------------------------------------------------------------- 287 * PISCR - Periodic Interrupt Status and Control 11-31 288 *----------------------------------------------------------------------- 289 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 290 */ 291#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) 292 293/*----------------------------------------------------------------------- 294 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 295 *----------------------------------------------------------------------- 296 * Reset PLL lock status sticky bit, timer expired status bit and timer 297 * interrupt status bit 298 */ 299 300/* for 64 MHz, we use a 16 MHz clock * 4 */ 301#define CONFIG_SYS_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) 302 303/*----------------------------------------------------------------------- 304 * SCCR - System Clock and reset Control Register 15-27 305 *----------------------------------------------------------------------- 306 * Set clock output, timebase and RTC source and divider, 307 * power management and some other internal clocks 308 */ 309#define SCCR_MASK SCCR_EBDF11 310#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_RTSEL | SCCR_RTDIV | \ 311 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 312 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 313 SCCR_DFALCD00) 314 315/*----------------------------------------------------------------------- 316 * PCMCIA stuff 317 *----------------------------------------------------------------------- 318 * 319 */ 320#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 321#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 322#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 323#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 324#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 325#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 326#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 327#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 328 329/*----------------------------------------------------------------------- 330 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 331 *----------------------------------------------------------------------- 332 */ 333 334#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 335#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 336 337#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 338#undef CONFIG_IDE_LED /* LED for ide not supported */ 339#undef CONFIG_IDE_RESET /* reset for ide not supported */ 340 341#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 342#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 343 344#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 345 346#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 347 348/* Offset for data I/O */ 349#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 350 351/* Offset for normal register accesses */ 352#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 353 354/* Offset for alternate registers */ 355#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 356 357/*----------------------------------------------------------------------- 358 * 359 *----------------------------------------------------------------------- 360 * 361 */ 362/*#define CONFIG_SYS_DER 0x2002000F*/ 363#define CONFIG_SYS_DER 0 364 365/* 366 * Init Memory Controller: 367 * 368 * BR0/1 (FLASH) 369 */ 370 371#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 372 373/* used to re-map FLASH both when starting from SRAM or FLASH: 374 * restrict access enough to keep SRAM working (if any) 375 * but not too much to meddle with FLASH accesses 376 */ 377#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 378#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 379 380/* 381 * FLASH timing: 382 */ 383/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ 384#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 385 OR_SCY_3_CLK | OR_EHTR | OR_BI) 386 387#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 388#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 389#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 390 391/* 392 * BR2/3 and OR2/3 (SDRAM) 393 * 394 */ 395#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 396#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 397#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 398 399/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 400#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 401 402#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 403#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 404 405#ifndef CONFIG_CAN_DRIVER 406#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 407#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 408#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 409#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 410#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 411#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 412#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 413 BR_PS_8 | BR_MS_UPMB | BR_V ) 414#endif /* CONFIG_CAN_DRIVER */ 415 416/* 417 * Memory Periodic Timer Prescaler 418 * 419 * The Divider for PTA (refresh timer) configuration is based on an 420 * example SDRAM configuration (64 MBit, one bank). The adjustment to 421 * the number of chip selects (NCS) and the actually needed refresh 422 * rate is done by setting MPTPR. 423 * 424 * PTA is calculated from 425 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 426 * 427 * gclk CPU clock (not bus clock!) 428 * Trefresh Refresh cycle * 4 (four word bursts used) 429 * 430 * 4096 Rows from SDRAM example configuration 431 * 1000 factor s -> ms 432 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 433 * 4 Number of refresh cycles per period 434 * 64 Refresh cycle in ms per number of rows 435 * -------------------------------------------- 436 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 437 * 438 * 50 MHz => 50.000.000 / Divider = 98 439 * 66 Mhz => 66.000.000 / Divider = 129 440 * 80 Mhz => 80.000.000 / Divider = 156 441 */ 442#define CONFIG_SYS_MAMR_PTA 129 443 444/* 445 * For 16 MBit, refresh rates could be 31.3 us 446 * (= 64 ms / 2K = 125 / quad bursts). 447 * For a simpler initialization, 15.6 us is used instead. 448 * 449 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 450 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 451 */ 452#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 453#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 454 455/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 456#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 457#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 458 459/* 460 * MAMR settings for SDRAM 461 */ 462 463/* 8 column SDRAM */ 464#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 465 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 467/* 9 column SDRAM */ 468#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 469 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 471 472 473#endif /* __CONFIG_H */ 474