1/* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 37#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ 38 39#define CONFIG_SYS_TEXT_BASE 0x40000000 40 41#ifdef CONFIG_LCD /* with LCD controller ? */ 42#define CONFIG_MPC8XX_LCD 43/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ 44#endif 45 46#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 47#define CONFIG_SYS_SMC_RXBUFLEN 128 48#define CONFIG_SYS_MAXIDLE 10 49#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 50 51#define CONFIG_BOOTCOUNT_LIMIT 52 53#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 54 55#define CONFIG_BOARD_TYPES 1 /* support board types */ 56 57#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 58 59#undef CONFIG_BOOTARGS 60 61#define CONFIG_EXTRA_ENV_SETTINGS \ 62 "netdev=eth0\0" \ 63 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 64 "nfsroot=${serverip}:${rootpath}\0" \ 65 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 66 "addip=setenv bootargs ${bootargs} " \ 67 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 68 ":${hostname}:${netdev}:off panic=1\0" \ 69 "flash_nfs=run nfsargs addip;" \ 70 "bootm ${kernel_addr}\0" \ 71 "flash_self=run ramargs addip;" \ 72 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 73 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 74 "rootpath=/opt/eldk/ppc_8xx\0" \ 75 "hostname=TQM823M\0" \ 76 "bootfile=TQM823M/uImage\0" \ 77 "fdt_addr=40080000\0" \ 78 "kernel_addr=400A0000\0" \ 79 "ramdisk_addr=40280000\0" \ 80 "u-boot=TQM823M/u-image.bin\0" \ 81 "load=tftp 200000 ${u-boot}\0" \ 82 "update=prot off 40000000 +${filesize};" \ 83 "era 40000000 +${filesize};" \ 84 "cp.b 200000 40000000 ${filesize};" \ 85 "sete filesize;save\0" \ 86 "" 87#define CONFIG_BOOTCOMMAND "run flash_self" 88 89#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 90#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 91 92#undef CONFIG_WATCHDOG /* watchdog disabled */ 93 94#ifdef CONFIG_LCD 95# undef CONFIG_STATUS_LED /* disturbs display */ 96#else 97# define CONFIG_STATUS_LED 1 /* Status LED enabled */ 98#endif /* CONFIG_LCD */ 99 100#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 101 102/* 103 * BOOTP options 104 */ 105#define CONFIG_BOOTP_SUBNETMASK 106#define CONFIG_BOOTP_GATEWAY 107#define CONFIG_BOOTP_HOSTNAME 108#define CONFIG_BOOTP_BOOTPATH 109#define CONFIG_BOOTP_BOOTFILESIZE 110 111 112#define CONFIG_MAC_PARTITION 113#define CONFIG_DOS_PARTITION 114 115#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 116 117 118/* 119 * Command line configuration. 120 */ 121#include <config_cmd_default.h> 122 123#define CONFIG_CMD_ASKENV 124#define CONFIG_CMD_DATE 125#define CONFIG_CMD_DHCP 126#define CONFIG_CMD_ELF 127#define CONFIG_CMD_EXT2 128#define CONFIG_CMD_IDE 129#define CONFIG_CMD_JFFS2 130#define CONFIG_CMD_NFS 131#define CONFIG_CMD_SNTP 132 133 134#define CONFIG_NETCONSOLE 135 136 137/* 138 * Miscellaneous configurable options 139 */ 140#define CONFIG_SYS_LONGHELP /* undef to save memory */ 141#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 142 143#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 144#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 145 146#if defined(CONFIG_CMD_KGDB) 147#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 148#else 149#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 150#endif 151#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 152#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 153#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 154 155#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 156#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 157 158#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 159 160#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 161 162/* 163 * Low Level Configuration Settings 164 * (address mappings, register initial values, etc.) 165 * You should know what you are doing if you make changes here. 166 */ 167/*----------------------------------------------------------------------- 168 * Internal Memory Mapped Register 169 */ 170#define CONFIG_SYS_IMMR 0xFFF00000 171 172/*----------------------------------------------------------------------- 173 * Definitions for initial stack pointer and data area (in DPRAM) 174 */ 175#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 176#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 177#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 178#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 179 180/*----------------------------------------------------------------------- 181 * Start addresses for the final memory configuration 182 * (Set up by the startup code) 183 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 184 */ 185#define CONFIG_SYS_SDRAM_BASE 0x00000000 186#define CONFIG_SYS_FLASH_BASE 0x40000000 187#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 188#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 189#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 190 191/* 192 * For booting Linux, the board info and command line data 193 * have to be in the first 8 MB of memory, since this is 194 * the maximum mapped by the Linux kernel during initialization. 195 */ 196#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 197 198/*----------------------------------------------------------------------- 199 * FLASH organization 200 */ 201 202/* use CFI flash driver */ 203#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 204#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 205#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 206#define CONFIG_SYS_FLASH_EMPTY_INFO 207#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 208#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 209#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 210 211#define CONFIG_ENV_IS_IN_FLASH 1 212#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 213#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 214#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 215 216/* Address and size of Redundant Environment Sector */ 217#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 218#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 219 220#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 221 222#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 223 224/*----------------------------------------------------------------------- 225 * Dynamic MTD partition support 226 */ 227#define CONFIG_CMD_MTDPARTS 228#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 229#define CONFIG_FLASH_CFI_MTD 230#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 231 232#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 233 "128k(dtb)," \ 234 "1920k(kernel)," \ 235 "5632(rootfs)," \ 236 "4m(data)" 237 238/*----------------------------------------------------------------------- 239 * Hardware Information Block 240 */ 241#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 242#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 243#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 244 245/*----------------------------------------------------------------------- 246 * Cache Configuration 247 */ 248#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 249#if defined(CONFIG_CMD_KGDB) 250#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 251#endif 252 253/*----------------------------------------------------------------------- 254 * SYPCR - System Protection Control 11-9 255 * SYPCR can only be written once after reset! 256 *----------------------------------------------------------------------- 257 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 258 */ 259#if defined(CONFIG_WATCHDOG) 260#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 261 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 262#else 263#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 264#endif 265 266/*----------------------------------------------------------------------- 267 * SIUMCR - SIU Module Configuration 11-6 268 *----------------------------------------------------------------------- 269 * PCMCIA config., multi-function pin tri-state 270 */ 271#ifndef CONFIG_CAN_DRIVER 272#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 273#else /* we must activate GPL5 in the SIUMCR for CAN */ 274#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 275#endif /* CONFIG_CAN_DRIVER */ 276 277/*----------------------------------------------------------------------- 278 * TBSCR - Time Base Status and Control 11-26 279 *----------------------------------------------------------------------- 280 * Clear Reference Interrupt Status, Timebase freezing enabled 281 */ 282#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 283 284/*----------------------------------------------------------------------- 285 * RTCSC - Real-Time Clock Status and Control Register 11-27 286 *----------------------------------------------------------------------- 287 */ 288#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 289 290/*----------------------------------------------------------------------- 291 * PISCR - Periodic Interrupt Status and Control 11-31 292 *----------------------------------------------------------------------- 293 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 294 */ 295#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 296 297/*----------------------------------------------------------------------- 298 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 299 *----------------------------------------------------------------------- 300 * Reset PLL lock status sticky bit, timer expired status bit and timer 301 * interrupt status bit 302 */ 303#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 304 305/*----------------------------------------------------------------------- 306 * SCCR - System Clock and reset Control Register 15-27 307 *----------------------------------------------------------------------- 308 * Set clock output, timebase and RTC source and divider, 309 * power management and some other internal clocks 310 */ 311#define SCCR_MASK SCCR_EBDF11 312#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 313 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 314 SCCR_DFALCD00) 315 316/*----------------------------------------------------------------------- 317 * PCMCIA stuff 318 *----------------------------------------------------------------------- 319 * 320 */ 321#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 322#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 323#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 324#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 325#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 326#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 327#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 328#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 329 330/*----------------------------------------------------------------------- 331 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 332 *----------------------------------------------------------------------- 333 */ 334 335#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 336#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 337 338#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 339#undef CONFIG_IDE_LED /* LED for ide not supported */ 340#undef CONFIG_IDE_RESET /* reset for ide not supported */ 341 342#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 343#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 344 345#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 346 347#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 348 349/* Offset for data I/O */ 350#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 351 352/* Offset for normal register accesses */ 353#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 354 355/* Offset for alternate registers */ 356#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 357 358/*----------------------------------------------------------------------- 359 * 360 *----------------------------------------------------------------------- 361 * 362 */ 363#define CONFIG_SYS_DER 0 364 365/* 366 * Init Memory Controller: 367 * 368 * BR0/1 and OR0/1 (FLASH) 369 */ 370 371#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 372#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 373 374/* used to re-map FLASH both when starting from SRAM or FLASH: 375 * restrict access enough to keep SRAM working (if any) 376 * but not too much to meddle with FLASH accesses 377 */ 378#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 379#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 380 381/* 382 * FLASH timing: 383 */ 384#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 385 OR_SCY_3_CLK | OR_EHTR | OR_BI) 386 387#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 388#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 389#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 390 391#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 392#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 393#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 394 395/* 396 * BR2/3 and OR2/3 (SDRAM) 397 * 398 */ 399#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 400#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 401#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 402 403/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 404#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 405 406#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 407#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 408 409#ifndef CONFIG_CAN_DRIVER 410#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 411#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 412#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 413#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 414#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 415#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 416#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 417 BR_PS_8 | BR_MS_UPMB | BR_V ) 418#endif /* CONFIG_CAN_DRIVER */ 419 420/* 421 * Memory Periodic Timer Prescaler 422 * 423 * The Divider for PTA (refresh timer) configuration is based on an 424 * example SDRAM configuration (64 MBit, one bank). The adjustment to 425 * the number of chip selects (NCS) and the actually needed refresh 426 * rate is done by setting MPTPR. 427 * 428 * PTA is calculated from 429 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 430 * 431 * gclk CPU clock (not bus clock!) 432 * Trefresh Refresh cycle * 4 (four word bursts used) 433 * 434 * 4096 Rows from SDRAM example configuration 435 * 1000 factor s -> ms 436 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 437 * 4 Number of refresh cycles per period 438 * 64 Refresh cycle in ms per number of rows 439 * -------------------------------------------- 440 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 441 * 442 * 50 MHz => 50.000.000 / Divider = 98 443 * 66 Mhz => 66.000.000 / Divider = 129 444 * 80 Mhz => 80.000.000 / Divider = 156 445 */ 446 447#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 448#define CONFIG_SYS_MAMR_PTA 98 449 450/* 451 * For 16 MBit, refresh rates could be 31.3 us 452 * (= 64 ms / 2K = 125 / quad bursts). 453 * For a simpler initialization, 15.6 us is used instead. 454 * 455 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 456 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 457 */ 458#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 459#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 460 461/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 462#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 463#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 464 465/* 466 * MAMR settings for SDRAM 467 */ 468 469/* 8 column SDRAM */ 470#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 471 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 472 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 473/* 9 column SDRAM */ 474#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 475 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 476 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 477 478/* pass open firmware flat tree */ 479#define CONFIG_OF_LIBFDT 1 480#define CONFIG_OF_BOARD_SETUP 1 481#define CONFIG_HWCONFIG 1 482 483#endif /* __CONFIG_H */ 484