1/* 2 * ICP DAS LP-8x4x configuration file 3 * 4 * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22#ifndef __CONFIG_H 23#define __CONFIG_H 24 25/* 26 * High Level Board Configuration Options 27 */ 28#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */ 29#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */ 30#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X 31#define CONFIG_SYS_TEXT_BASE 0x00000000 32 33#define CONFIG_SYS_MALLOC_LEN (128*1024) 34#define CONFIG_ARCH_CPU_INIT 35#define CONFIG_BOOTCOMMAND \ 36 "bootm 80000;" 37 38#define CONFIG_BOOTARGS \ 39 "console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \ 40 "init=/sbin/init rootfstype=ext3" 41 42#define CONFIG_TIMESTAMP 43#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ 44#define CONFIG_CMDLINE_TAG 45#define CONFIG_SETUP_MEMORY_TAGS 46#define CONFIG_LZMA /* LZMA compression support */ 47#undef CONFIG_OF_LIBFDT 48 49/* 50 * Serial Console Configuration 51 */ 52#define CONFIG_PXA_SERIAL 53#define CONFIG_FFUART 1 54#define CONFIG_CONS_INDEX 3 55#define CONFIG_BAUDRATE 115200 56 57/* 58 * Bootloader Components Configuration 59 */ 60#include <config_cmd_default.h> 61 62#define CONFIG_CMD_NET 63#define CONFIG_CMD_ENV 64#undef CONFIG_CMD_IMLS 65#define CONFIG_CMD_MMC 66#define CONFIG_CMD_USB 67#undef CONFIG_LCD 68#undef CONFIG_CMD_IDE 69 70/* 71 * Networking Configuration 72 * chip on the ICPDAS LINPAC board 73 */ 74#ifdef CONFIG_CMD_NET 75#define CONFIG_CMD_PING 76#define CONFIG_CMD_DHCP 77 78#define CONFIG_DRIVER_DM9000 1 79#define CONFIG_DM9000_BASE 0x0C000000 80#define DM9000_IO 0x0C000000 81#define DM9000_DATA 0x0C004000 82#define DM9000_IO_2 0x0D000000 83#define DM9000_DATA_2 0x0D004000 84#define CONFIG_NET_RETRY_COUNT 10 85 86#define CONFIG_BOOTP_BOOTFILESIZE 87#define CONFIG_BOOTP_BOOTPATH 88#define CONFIG_BOOTP_GATEWAY 89#define CONFIG_BOOTP_HOSTNAME 90#endif 91 92/* 93 * MMC Card Configuration 94 */ 95#ifdef CONFIG_CMD_MMC 96#define CONFIG_MMC 97#define CONFIG_GENERIC_MMC 98#define CONFIG_PXA_MMC_GENERIC 99#define CONFIG_CMD_FAT 100#define CONFIG_CMD_EXT2 101#define CONFIG_DOS_PARTITION 102#endif 103 104/* 105 * KGDB 106 */ 107#ifdef CONFIG_CMD_KGDB 108#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ 109#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 110#endif 111 112/* 113 * HUSH Shell Configuration 114 */ 115#define CONFIG_SYS_HUSH_PARSER 1 116 117#undef CONFIG_SYS_LONGHELP 118#ifdef CONFIG_SYS_HUSH_PARSER 119#define CONFIG_SYS_PROMPT "$ " 120#else 121#define CONFIG_SYS_PROMPT "=> " 122#endif 123#define CONFIG_SYS_CBSIZE 256 124#define CONFIG_SYS_PBSIZE \ 125 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 126#define CONFIG_SYS_MAXARGS 16 127#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 128#define CONFIG_SYS_DEVICE_NULLDEV 1 129#define CONFIG_CMDLINE_EDITING 1 130#define CONFIG_AUTO_COMPLETE 1 131 132/* 133 * Clock Configuration 134 */ 135#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ 136 137/* 138 * DRAM Map 139 */ 140#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ 141#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 142#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 143 144#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 145#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ 146 147#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 148#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 149 150#define CONFIG_SYS_LOAD_ADDR 0xa0008000 151#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 152/* Use first 64kb bank of the internal SRAM */ 153#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 154 155/* 156 * NOR FLASH 157 */ 158#define CONFIG_SYS_MONITOR_BASE 0x0 159#define CONFIG_SYS_MONITOR_LEN 0x40000 160#define CONFIG_ENV_ADDR \ 161 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 162#define CONFIG_ENV_SIZE 0x40000 163#define CONFIG_ENV_SECT_SIZE 0x40000 164 165#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 166#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ 167 168#define CONFIG_SYS_FLASH_CFI 169#define CONFIG_FLASH_CFI_DRIVER 1 170 171#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) 172#define CONFIG_SYS_MAX_FLASH_BANKS 2 173#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } 174 175#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) 176#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) 177 178#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 179#define CONFIG_SYS_FLASH_PROTECTION 1 180 181#define CONFIG_ENV_IS_IN_FLASH 1 182 183/* 184 * GPIO settings 185 */ 186#define CONFIG_SYS_GPSR0_VAL 0x0808c014 187#define CONFIG_SYS_GPSR1_VAL 0x00cf0002 188#define CONFIG_SYS_GPSR2_VAL 0x0221c000 189#define CONFIG_SYS_GPSR3_VAL 0x00020000 190 191#define CONFIG_SYS_GPCR0_VAL 0x00000000 192#define CONFIG_SYS_GPCR1_VAL 0x0000ab80 193#define CONFIG_SYS_GPCR2_VAL 0x00100000 194#define CONFIG_SYS_GPCR3_VAL 0x0 195 196#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4 197#define CONFIG_SYS_GPDR1_VAL 0xfcffab83 198#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff 199#define CONFIG_SYS_GPDR3_VAL 0x00021b81 200 201#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 202#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018 203#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a 204#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a 205#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa 206#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402 207#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c 208#define CONFIG_SYS_GAFR3_U_VAL 0x00001599 209 210#define CONFIG_SYS_PSSR_VAL 0x32 211 212/* 213 * Clock settings 214 */ 215#define CONFIG_SYS_CKEN 0x005002c0 216#define CONFIG_SYS_CCCR 0x02000290 217#define CONFIG_SYS_CLKCFG 0x0000000b 218 219/* 220 * Memory settings 221 */ 222#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2 223#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc 224#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9 225#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 226#define CONFIG_SYS_MDREFR_VAL 0x2093e018 227#define CONFIG_SYS_MDCNFG_VAL 0x890009d1 228#define CONFIG_SYS_MDMRS_VAL 0x00220022 229#define CONFIG_SYS_SXCNFG_VAL 0x40044004 230 231/* 232 * PCMCIA and CF Interfaces 233 */ 234#define CONFIG_SYS_MECR_VAL 0x00000001 235#define CONFIG_SYS_MCMEM0_VAL 0x0000c497 236#define CONFIG_SYS_MCMEM1_VAL 0x0000c497 237#define CONFIG_SYS_MCATT0_VAL 0x0000c497 238#define CONFIG_SYS_MCATT1_VAL 0x0000c497 239#define CONFIG_SYS_MCIO0_VAL 0x00008407 240#define CONFIG_SYS_MCIO1_VAL 0x00008407 241 242/* 243 * LCD 244 */ 245#ifdef CONFIG_LCD 246#define CONFIG_VOIPAC_LCD 247#endif 248 249/* 250 * USB 251 */ 252#ifdef CONFIG_CMD_USB 253#define CONFIG_USB_OHCI_NEW 254#define CONFIG_SYS_USB_OHCI_CPU_INIT 255#define CONFIG_SYS_USB_OHCI_BOARD_INIT 256#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 257#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 258#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x" 259#define CONFIG_USB_STORAGE 260#endif 261 262#endif /* __CONFIG_H */ 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