1/* 2 * (C) Copyright 2009 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#ifndef __MANROLAND_MPC52XX__COMMON_H 25#define __MANROLAND_MPC52XX__COMMON_H 26 27/* 28 * High Level Configuration Options 29 * (easy to change) 30 */ 31#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ 32#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ 33 34#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 35 36#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 37 38/* 39 * Serial console configuration 40 */ 41#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 42#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\ 43 230400 } 44 45#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */ 46# define CONFIG_SYS_LOWBOOT 1 47#endif 48 49/* 50 * IPB Bus clocking configuration. 51 */ 52#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 53 54/* 55 * I2C configuration 56 */ 57#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 58#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 59 60#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 61#define CONFIG_SYS_I2C_SLAVE 0x7F 62 63/* 64 * EEPROM configuration 65 */ 66#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 67#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 68#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 69#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 70 71/* 72 * RTC configuration 73 */ 74#define CONFIG_RTC_PCF8563 75#define CONFIG_SYS_I2C_RTC_ADDR 0x51 76 77/* I2C SYSMON (LM75) */ 78#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ 79#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 80#define CONFIG_SYS_DTT_MAX_TEMP 70 81#define CONFIG_SYS_DTT_LOW_TEMP -30 82#define CONFIG_SYS_DTT_HYSTERESIS 3 83 84/* 85 * Flash configuration 86 */ 87#define CONFIG_SYS_FLASH_BASE 0xFF800000 88 89#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ 90 91#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */ 92#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks 93 (= chip selects) */ 94#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/ 95#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/ 96 97#define CONFIG_FLASH_CFI_DRIVER 98#define CONFIG_SYS_FLASH_CFI 99#define CONFIG_SYS_FLASH_EMPTY_INFO 100#define CONFIG_SYS_FLASH_CFI_AMD_RESET 101 102/* 103 * Environment settings 104 */ 105#define CONFIG_ENV_IS_IN_FLASH 1 106#define CONFIG_ENV_SIZE 0x4000 107#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 108#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 109 110/* 111 * Memory map 112 */ 113#define CONFIG_SYS_MBAR 0xF0000000 114#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 115 116#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ 117 GENERATED_GBL_DATA_SIZE) 118#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 119 120#define CONFIG_SYS_SDRAM_BASE 0x00000000 121#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */ 122#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */ 123 124/* Settings for XLB = 132 MHz */ 125#define SDRAM_DDR 1 126#define SDRAM_MODE 0x018D0000 127#define SDRAM_EMODE 0x40090000 128#define SDRAM_CONTROL 0x714f0f00 129#define SDRAM_CONFIG1 0x73722930 130#define SDRAM_CONFIG2 0x47770000 131#define SDRAM_TAPDELAY 0x10000000 132 133/* Use ON-Chip SRAM until RAM will be available */ 134#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 135#ifdef CONFIG_POST 136/* preserve space for the post_word at end of on-chip SRAM */ 137#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE 138#else 139#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE 140#endif 141 142#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 143#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 144# define CONFIG_SYS_RAMBOOT 1 145#endif 146 147#define CONFIG_SYS_MONITOR_LEN (192 << 10) 148#define CONFIG_SYS_MALLOC_LEN (512 << 10) 149#define CONFIG_SYS_BOOTMAPSZ (8 << 20) 150 151/* 152 * Ethernet configuration 153 */ 154#define CONFIG_MPC5xxx_FEC 1 155#define CONFIG_MPC5xxx_FEC_MII100 156#define CONFIG_PHY_ADDR 0x00 157#define CONFIG_MII 1 158 159/*use Hardware WDT */ 160#define CONFIG_HW_WATCHDOG 161 162#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 163 164#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 165#if defined(CONFIG_CMD_KGDB) 166# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ 167#endif 168 169/* 170 * Various low-level settings 171 */ 172#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 173#define CONFIG_SYS_HID0_FINAL HID0_ICE 174 175#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 176#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 177#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 178#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 179 180/* 8Mbit SRAM @0x80100000 */ 181#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE 182 183#define CONFIG_SYS_CS_BURST 0x00000000 184#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 185 186/*----------------------------------------------------------------------- 187 * IDE/ATA stuff Supports IDE harddisk 188 *----------------------------------------------------------------------- 189 */ 190 191#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 192 193#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 194#undef CONFIG_IDE_LED /* LED for ide not supported */ 195 196#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 197 198#define CONFIG_IDE_PREINIT 1 199 200#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 201 202#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 203 204/* Offset for data I/O */ 205#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 206 207/* Offset for normal register accesses */ 208#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 209 210/* Offset for alternate registers */ 211#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 212 213/* Interval between registers */ 214#define CONFIG_SYS_ATA_STRIDE 4 215 216#define CONFIG_ATAPI 1 217 218#define OF_CPU "PowerPC,5200@0" 219#define OF_SOC "soc5200@f0000000" 220#define OF_TBCLK (bd->bi_busfreq / 4) 221#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" 222#define CONFIG_OF_IDE_FIXUP 223 224#endif /* __MANROLAND_MPC52XX__COMMON_H */ 225