1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39
40#define CONFIG_MPC86xx 1
41#define CONFIG_MPC8641 1
42#define CONFIG_SBC8641D 1
43#define CONFIG_MP 1
44#define CONFIG_LINUX_RESET_VEC 0x100
45
46#define CONFIG_SYS_TEXT_BASE 0xfff00000
47
48#ifdef RUN_DIAG
49#define CONFIG_SYS_DIAG_ADDR 0xff800000
50#endif
51
52#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
53
54
55
56
57
58#define CONFIG_SYS_SCRATCH_VA 0xe8000000
59
60#define CONFIG_SYS_SRIO
61#define CONFIG_SRIO1
62
63#define CONFIG_PCI 1
64#define CONFIG_PCIE1 1
65#define CONFIG_PCIE2 1
66#define CONFIG_FSL_PCI_INIT 1
67#define CONFIG_PCI_INDIRECT_BRIDGE 1
68#define CONFIG_FSL_LAW 1
69
70#define CONFIG_TSEC_ENET
71#define CONFIG_ENV_OVERWRITE
72
73#define CONFIG_BAT_RW 1
74#define CONFIG_HIGH_BATS 1
75
76#undef CONFIG_SPD_EEPROM
77#undef CONFIG_DDR_ECC
78#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
79#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
80#define CONFIG_NUM_DDR_CONTROLLERS 2
81#define CACHE_LINE_INTERLEAVING 0x20000000
82#define PAGE_INTERLEAVING 0x21000000
83#define BANK_INTERLEAVING 0x22000000
84#define SUPER_BANK_INTERLEAVING 0x23000000
85
86
87#define CONFIG_ALTIVEC 1
88
89
90
91
92#define CONFIG_SYS_L2
93#define L2_INIT 0
94#define L2_ENABLE (L2CR_L2E)
95
96#ifndef CONFIG_SYS_CLK_FREQ
97#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
98#endif
99
100#define CONFIG_BOARD_EARLY_INIT_F 1
101
102#undef CONFIG_SYS_DRAM_TEST
103#define CONFIG_SYS_MEMTEST_START 0x00200000
104#define CONFIG_SYS_MEMTEST_END 0x00400000
105
106
107
108
109
110#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
111#define CONFIG_SYS_CCSRBAR 0xf8000000
112#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
113
114#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
115#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
116#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
117
118
119
120
121#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
122#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000
123#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
124#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
125#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
126#define CONFIG_VERY_BIG_RAM
127
128#define CONFIG_NUM_DDR_CONTROLLERS 2
129#define CONFIG_DIMM_SLOTS_PER_CTLR 2
130#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
131
132#if defined(CONFIG_SPD_EEPROM)
133
134
135
136 #define SPD_EEPROM_ADDRESS1 0x51
137 #define SPD_EEPROM_ADDRESS2 0x52
138 #define SPD_EEPROM_ADDRESS3 0x53
139 #define SPD_EEPROM_ADDRESS4 0x54
140
141#else
142
143
144
145
146 #define CONFIG_SYS_SDRAM_SIZE 512
147
148 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
149 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
150 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
151 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
152 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
153 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
154 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
155 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
156 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
157 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
158 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
159 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
160 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
161 #define CONFIG_SYS_DDR_CFG_2 0x24401000
162 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
163 #define CONFIG_SYS_DDR_MODE_2 0x00000000
164 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
165 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
166 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
167 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
168 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
169
170 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
171 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
172 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
173 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
174 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
175 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
176 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
177 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
178 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
179 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
180 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
181 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
182 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
183 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
184 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
185 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
186 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
187 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
188 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
189 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
190 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
191
192
193#endif
194
195
196
197
198
199
200
201#define CONFIG_SYS_FLASH_BASE 0xff000000
202
203
204#define CONFIG_SYS_BR0_PRELIM 0xff001001
205#define CONFIG_SYS_OR0_PRELIM 0xff006e65
206
207
208#define CONFIG_SYS_BR1_PRELIM 0xf0000801
209#define CONFIG_SYS_OR1_PRELIM 0xffff6e65
210
211
212#define CONFIG_SYS_BR2_PRELIM 0xf1000801
213#define CONFIG_SYS_OR2_PRELIM 0xfff06e65
214
215
216#define CONFIG_SYS_BR3_PRELIM 0xe0001861
217#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
218#define CONFIG_SYS_BR4_PRELIM 0xe4001861
219#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
220
221
222#define CONFIG_SYS_BR5_PRELIM 0xe8001001
223#define CONFIG_SYS_OR5_PRELIM 0xf8006e65
224
225
226#define CONFIG_SYS_BR6_PRELIM 0xf4000801
227#define CONFIG_SYS_OR6_PRELIM 0xfff06e65
228
229
230#define CONFIG_SYS_BR7_PRELIM 0xf2000801
231#define CONFIG_SYS_OR7_PRELIM 0xfff06e65
232
233#define CONFIG_SYS_MAX_FLASH_BANKS 1
234#define CONFIG_SYS_MAX_FLASH_SECT 131
235
236#undef CONFIG_SYS_FLASH_CHECKSUM
237#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
238#define CONFIG_SYS_FLASH_WRITE_TOUT 500
239#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
240#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
241
242#define CONFIG_FLASH_CFI_DRIVER
243#define CONFIG_SYS_FLASH_CFI
244#define CONFIG_SYS_WRITE_SWAPPED_DATA
245#define CONFIG_SYS_FLASH_EMPTY_INFO
246#define CONFIG_SYS_FLASH_PROTECTION
247
248#undef CONFIG_CLOCKS_IN_MHZ
249
250#define CONFIG_SYS_INIT_RAM_LOCK 1
251#ifndef CONFIG_SYS_INIT_RAM_LOCK
252#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000
253#else
254#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000
255#endif
256#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
257
258#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
259#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
260
261#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
262#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
263
264
265#define CONFIG_CONS_INDEX 1
266#define CONFIG_SYS_NS16550
267#define CONFIG_SYS_NS16550_SERIAL
268#define CONFIG_SYS_NS16550_REG_SIZE 1
269#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
270
271#define CONFIG_SYS_BAUDRATE_TABLE \
272 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
273
274#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
275#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
276
277
278#define CONFIG_SYS_HUSH_PARSER
279#ifdef CONFIG_SYS_HUSH_PARSER
280#endif
281
282
283
284
285#define CONFIG_OF_LIBFDT 1
286#define CONFIG_OF_BOARD_SETUP 1
287#define CONFIG_OF_STDOUT_VIA_ALIAS 1
288
289
290
291
292#define CONFIG_FSL_I2C
293#define CONFIG_HARD_I2C
294#undef CONFIG_SOFT_I2C
295#define CONFIG_SYS_I2C_SPEED 400000
296#define CONFIG_SYS_I2C_SLAVE 0x7F
297#define CONFIG_SYS_I2C_NOPROBES {0x69}
298#define CONFIG_SYS_I2C_OFFSET 0x3100
299
300
301
302
303#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000
304#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
305#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
306
307
308
309
310
311#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
312#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
313#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
314#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
315#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
316#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
317#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
318#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000
319
320#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
321#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
322#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
323#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
324#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
325#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
326#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
327#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000
328
329#if defined(CONFIG_PCI)
330
331#define CONFIG_PCI_SCAN_SHOW
332
333#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
334
335#define CONFIG_PCI_PNP
336
337#undef CONFIG_EEPRO100
338#undef CONFIG_TULIP
339
340#if !defined(CONFIG_PCI_PNP)
341 #define PCI_ENET0_IOADDR 0xe0000000
342 #define PCI_ENET0_MEMADDR 0xe0000000
343 #define PCI_IDSEL_NUMBER 0x0c
344#endif
345
346#define CONFIG_PCI_SCAN_SHOW
347
348#define CONFIG_DOS_PARTITION
349#undef CONFIG_SCSI_AHCI
350
351#ifdef CONFIG_SCSI_AHCI
352#define CONFIG_SATA_ULI5288
353#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
354#define CONFIG_SYS_SCSI_MAX_LUN 1
355#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
356#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
357#endif
358
359#endif
360
361#if defined(CONFIG_TSEC_ENET)
362
363
364
365#define CONFIG_TSEC1 1
366#define CONFIG_TSEC1_NAME "eTSEC1"
367#define CONFIG_TSEC2 1
368#define CONFIG_TSEC2_NAME "eTSEC2"
369#define CONFIG_TSEC3 1
370#define CONFIG_TSEC3_NAME "eTSEC3"
371#define CONFIG_TSEC4 1
372#define CONFIG_TSEC4_NAME "eTSEC4"
373
374#define TSEC1_PHY_ADDR 0x1F
375#define TSEC2_PHY_ADDR 0x00
376#define TSEC3_PHY_ADDR 0x01
377#define TSEC4_PHY_ADDR 0x02
378#define TSEC1_PHYIDX 0
379#define TSEC2_PHYIDX 0
380#define TSEC3_PHYIDX 0
381#define TSEC4_PHYIDX 0
382#define TSEC1_FLAGS TSEC_GIGABIT
383#define TSEC2_FLAGS TSEC_GIGABIT
384#define TSEC3_FLAGS TSEC_GIGABIT
385#define TSEC4_FLAGS TSEC_GIGABIT
386
387#define CONFIG_SYS_TBIPA_VALUE 0x1e
388
389#define CONFIG_ETHPRIME "eTSEC1"
390
391#endif
392
393
394
395
396
397#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
398#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
399#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
400#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
401
402
403
404
405
406
407
408#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
409 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
410#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
411#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
412#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
413
414
415
416
417
418#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
419 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
420#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
421#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
422#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
423
424
425
426
427
428#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
429 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
430#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
431#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
432#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
433
434#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
435#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
436 | BATL_PP_RW | BATL_CACHEINHIBIT \
437 | BATL_GUARDEDSTORAGE)
438#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
439 | BATU_BL_1M | BATU_VS | BATU_VP)
440#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
441 | BATL_PP_RW | BATL_CACHEINHIBIT)
442#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
443#endif
444
445
446
447
448
449
450
451#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
452 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
453#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
454#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
455#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
456
457
458
459
460
461#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
462#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
463#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
464#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
465
466
467
468
469
470#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
471 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
472#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
473#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
474#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
475
476
477#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
478 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
479#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
480#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
481 | BATL_MEMCOHERENCE)
482#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
483
484#define CONFIG_SYS_DBAT7L 0x00000000
485#define CONFIG_SYS_DBAT7U 0x00000000
486#define CONFIG_SYS_IBAT7L 0x00000000
487#define CONFIG_SYS_IBAT7U 0x00000000
488
489
490
491
492#define CONFIG_ENV_IS_IN_FLASH 1
493#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
494#define CONFIG_ENV_SECT_SIZE 0x40000
495#define CONFIG_ENV_SIZE 0x2000
496
497#define CONFIG_LOADS_ECHO 1
498#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
499
500#include <config_cmd_default.h>
501 #define CONFIG_CMD_PING
502 #define CONFIG_CMD_I2C
503 #define CONFIG_CMD_REGINFO
504
505#if defined(CONFIG_PCI)
506 #define CONFIG_CMD_PCI
507#endif
508
509#undef CONFIG_WATCHDOG
510
511
512
513
514#define CONFIG_SYS_LONGHELP
515#define CONFIG_SYS_LOAD_ADDR 0x2000000
516#define CONFIG_SYS_PROMPT "=> "
517
518#if defined(CONFIG_CMD_KGDB)
519 #define CONFIG_SYS_CBSIZE 1024
520#else
521 #define CONFIG_SYS_CBSIZE 256
522#endif
523
524#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
525#define CONFIG_SYS_MAXARGS 16
526#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
527#define CONFIG_SYS_HZ 1000
528
529
530
531
532
533
534#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
535
536
537#define CONFIG_SYS_DCACHE_SIZE 32768
538#define CONFIG_SYS_CACHELINE_SIZE 32
539#if defined(CONFIG_CMD_KGDB)
540#define CONFIG_SYS_CACHELINE_SHIFT 5
541#endif
542
543#if defined(CONFIG_CMD_KGDB)
544#define CONFIG_KGDB_BAUDRATE 230400
545#define CONFIG_KGDB_SER_INDEX 2
546#endif
547
548
549
550
551
552
553#if defined(CONFIG_TSEC_ENET)
554#define CONFIG_ETHADDR 02:E0:0C:00:00:01
555#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
556#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
557#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
558#endif
559
560#define CONFIG_HAS_ETH0 1
561#define CONFIG_HAS_ETH1 1
562#define CONFIG_HAS_ETH2 1
563#define CONFIG_HAS_ETH3 1
564
565#define CONFIG_IPADDR 192.168.0.50
566
567#define CONFIG_HOSTNAME sbc8641d
568#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
569#define CONFIG_BOOTFILE "uImage"
570
571#define CONFIG_SERVERIP 192.168.0.2
572#define CONFIG_GATEWAYIP 192.168.0.1
573#define CONFIG_NETMASK 255.255.255.0
574
575
576#define CONFIG_LOADADDR 1000000
577
578#define CONFIG_BOOTDELAY 10
579#undef CONFIG_BOOTARGS
580
581#define CONFIG_BAUDRATE 115200
582
583#define CONFIG_EXTRA_ENV_SETTINGS \
584 "netdev=eth0\0" \
585 "consoledev=ttyS0\0" \
586 "ramdiskaddr=2000000\0" \
587 "ramdiskfile=uRamdisk\0" \
588 "dtbaddr=400000\0" \
589 "dtbfile=sbc8641d.dtb\0" \
590 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
591 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
592 "maxcpus=1"
593
594#define CONFIG_NFSBOOTCOMMAND \
595 "setenv bootargs root=/dev/nfs rw " \
596 "nfsroot=$serverip:$rootpath " \
597 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
598 "console=$consoledev,$baudrate $othbootargs;" \
599 "tftp $loadaddr $bootfile;" \
600 "tftp $dtbaddr $dtbfile;" \
601 "bootm $loadaddr - $dtbaddr"
602
603#define CONFIG_RAMBOOTCOMMAND \
604 "setenv bootargs root=/dev/ram rw " \
605 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
606 "console=$consoledev,$baudrate $othbootargs;" \
607 "tftp $ramdiskaddr $ramdiskfile;" \
608 "tftp $loadaddr $bootfile;" \
609 "tftp $dtbaddr $dtbfile;" \
610 "bootm $loadaddr $ramdiskaddr $dtbaddr"
611
612#define CONFIG_FLASHBOOTCOMMAND \
613 "setenv bootargs root=/dev/ram rw " \
614 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
615 "console=$consoledev,$baudrate $othbootargs;" \
616 "bootm ffd00000 ffb00000 ffa00000"
617
618#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
619
620#endif
621