1/* 2 * (C) Copyright 2004-2005 3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 4 * 5 * (C) Copyright 2004 6 * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com 7 * 8 * (C) Copyright 2002 9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne 10 * 11 * (C) Copyright 2002 12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 13 * Marius Groeger <mgroeger@sysgo.de> 14 * 15 * Configuation settings for the xaeniax board. 16 * 17 * See file CREDITS for list of people who contributed to this 18 * project. 19 * 20 * This program is free software; you can redistribute it and/or 21 * modify it under the terms of the GNU General Public License as 22 * published by the Free Software Foundation; either version 2 of 23 * the License, or (at your option) any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; if not, write to the Free Software 32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 33 * MA 02111-1307 USA 34 */ 35 36#ifndef __CONFIG_H 37#define __CONFIG_H 38 39/* 40 * High Level Configuration Options 41 * (easy to change) 42 */ 43#define CONFIG_CPU_PXA25X 1 /* This is an PXA255 CPU */ 44#define CONFIG_XAENIAX 1 /* on a xaeniax board */ 45#define CONFIG_SYS_TEXT_BASE 0x0 46 47#define CONFIG_BOARD_LATE_INIT 48 49/* we will never enable dcache, because we have to setup MMU first */ 50#define CONFIG_SYS_DCACHE_OFF 51 52/* 53 * select serial console configuration 54 */ 55#define CONFIG_PXA_SERIAL 56#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */ 57#define CONFIG_CONS_INDEX 4 58 59/* allow to overwrite serial and ethaddr */ 60#define CONFIG_ENV_OVERWRITE 61 62#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 63 64#define CONFIG_BAUDRATE 115200 65 66/* 67 * BOOTP options 68 */ 69#define CONFIG_BOOTP_BOOTFILESIZE 70#define CONFIG_BOOTP_BOOTPATH 71#define CONFIG_BOOTP_GATEWAY 72#define CONFIG_BOOTP_HOSTNAME 73 74 75/* 76 * Command line configuration. 77 */ 78#include <config_cmd_default.h> 79 80#define CONFIG_CMD_DHCP 81#define CONFIG_CMD_DIAG 82#define CONFIG_CMD_NFS 83#define CONFIG_CMD_SDRAM 84#define CONFIG_CMD_SNTP 85 86#undef CONFIG_CMD_DTT 87 88 89#define CONFIG_ETHADDR 08:00:3e:26:0a:5b 90#define CONFIG_NETMASK 255.255.255.0 91#define CONFIG_IPADDR 192.168.68.201 92#define CONFIG_SERVERIP 192.168.68.62 93 94#define CONFIG_BOOTDELAY 3 95#define CONFIG_BOOTCOMMAND "bootm 0x00100000" 96#define CONFIG_BOOTARGS "console=ttyS1,115200" 97#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 98#define CONFIG_SETUP_MEMORY_TAGS 1 99#define CONFIG_INITRD_TAG 1 100 101#if defined(CONFIG_CMD_KGDB) 102#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ 103#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ 104#endif 105 106/* 107 * Size of malloc() pool; this lives below the uppermost 128 KiB which are 108 * used for the RAM copy of the uboot code 109 */ 110#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 111 112/* 113 * Miscellaneous configurable options 114 */ 115#define CONFIG_SYS_LONGHELP /* undef to save memory */ 116#define CONFIG_SYS_HUSH_PARSER 1 117 118 119#ifdef CONFIG_SYS_HUSH_PARSER 120#define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */ 121#else 122#define CONFIG_SYS_PROMPT "u-boot=> " /* Monitor Command Prompt */ 123#endif 124#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 125#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 126#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 127#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 128#define CONFIG_SYS_DEVICE_NULLDEV 1 129 130#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 131#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 132 133#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ 134 135#define CONFIG_SYS_HZ 1000 136#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ 137 138/* 139 * Physical Memory Map 140 */ 141#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */ 142#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 143#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 144#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ 145#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ 146#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ 147#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ 148#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ 149#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ 150 151#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 152#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ 153#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 154#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ 155#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ 156 157#define CONFIG_SYS_DRAM_BASE 0xa0000000 158#define CONFIG_SYS_DRAM_SIZE 0x04000000 159 160#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 161 162#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 163#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 164 165/* 166 * FLASH and environment organization 167 */ 168#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 169#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 170 171/* timeout values are in ticks */ 172#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 173#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 174 175/* FIXME */ 176#define CONFIG_ENV_IS_IN_FLASH 1 177#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */ 178#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ 179 180/* 181 * SMSC91C111 Network Card 182 */ 183#define CONFIG_SMC91111 1 184#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */ 185#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ 186#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ 187#undef CONFIG_SHOW_ACTIVITY 188#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ 189 190/* 191 * GPIO settings 192 */ 193 194/* 195 * GP05 == nUSBReset is 1 196 * GP10 == CFReset is 1 197 * GP13 == nCFDataEnable is 1 198 * GP14 == nCFAddrEnable is 1 199 * GP15 == nCS1 is 1 200 * GP21 == ComBrdReset is 1 201 * GP24 == SFRM is 1 202 * GP25 == TXD is 1 203 * GP31 == SYNC is 1 204 * GP33 == nCS5 is 1 205 * GP39 == FFTXD is 1 206 * GP41 == RTS is 1 207 * GP43 == BTTXD is 1 208 * GP45 == BTRTS is 1 209 * GP47 == TXD is 1 210 * GP48 == nPOE is 1 211 * GP49 == nPWE is 1 212 * GP50 == nPIOR is 1 213 * GP51 == nPIOW is 1 214 * GP52 == nPCE[1] is 1 215 * GP53 == nPCE[2] is 1 216 * GP54 == nPSKTSEL is 1 217 * GP55 == nPREG is 1 218 * GP78 == nCS2 is 1 219 * GP79 == nCS3 is 1 220 * GP80 == nCS4 is 1 221 * GP82 == NSSPSFRM is 1 222 * GP83 == NSSPTXD is 1 223 */ 224#define CONFIG_SYS_GPSR0_VAL 0x8320E420 225#define CONFIG_SYS_GPSR1_VAL 0x00FFAA82 226#define CONFIG_SYS_GPSR2_VAL 0x000DC000 227 228/* 229 * GP03 == LANReset is 0 230 * GP06 == USBWakeUp is 0 231 * GP11 == USBControl is 0 232 * GP12 == Buzzer is 0 233 * GP16 == PWM0 is 0 234 * GP17 == PWM1 is 0 235 * GP23 == SCLK is 0 236 * GP30 == SDATA_OUT is 0 237 * GP81 == NSSPCLK is 0 238 */ 239#define CONFIG_SYS_GPCR0_VAL 0x40C31848 240#define CONFIG_SYS_GPCR1_VAL 0x00000000 241#define CONFIG_SYS_GPCR2_VAL 0x00020000 242 243/* 244 * GP00 == CPUWakeUpUSB is input 245 * GP01 == GP reset is input 246 * GP02 == LANInterrupt is input 247 * GP03 == LANReset is output 248 * GP04 == USBInterrupt is input 249 * GP05 == nUSBReset is output 250 * GP06 == USBWakeUp is output 251 * GP07 == CFReady/nBusy is input 252 * GP08 == nCFCardDetect1 is input 253 * GP09 == nCFCardDetect2 is input 254 * GP10 == nCFReset is output 255 * GP11 == USBControl is output 256 * GP12 == Buzzer is output 257 * GP13 == CFDataEnable is output 258 * GP14 == CFAddressEnable is output 259 * GP15 == nCS1 is output 260 * GP16 == PWM0 is output 261 * GP17 == PWM1 is output 262 * GP18 == RDY is input 263 * GP19 == ReaderReady is input 264 * GP20 == ReaderReset is input 265 * GP21 == ComBrdReset is output 266 * GP23 == SCLK is output 267 * GP24 == SFRM is output 268 * GP25 == TXD is output 269 * GP26 == RXD is input 270 * GP27 == EXTCLK is input 271 * GP28 == BITCLK is output 272 * GP29 == SDATA_IN0 is input 273 * GP30 == SDATA_OUT is output 274 * GP31 == SYNC is output 275 * GP32 == SYSSCLK is output 276 * GP33 == nCS5 is output 277 * GP34 == FFRXD is input 278 * GP35 == CTS is input 279 * GP36 == DCD is input 280 * GP37 == DSR is input 281 * GP38 == RI is input 282 * GP39 == FFTXD is output 283 * GP40 == DTR is output 284 * GP41 == RTS is output 285 * GP42 == BTRXD is input 286 * GP43 == BTTXD is output 287 * GP44 == BTCTS is input 288 * GP45 == BTRTS is output 289 * GP46 == RXD is input 290 * GP47 == TXD is output 291 * GP48 == nPOE is output 292 * GP49 == nPWE is output 293 * GP50 == nPIOR is output 294 * GP51 == nPIOW is output 295 * GP52 == nPCE[1] is output 296 * GP53 == nPCE[2] is output 297 * GP54 == nPSKTSEL is output 298 * GP55 == nPREG is output 299 * GP56 == nPWAIT is input 300 * GP57 == nPIOS16 is input 301 * GP58 == LDD[0] is output 302 * GP59 == LDD[1] is output 303 * GP60 == LDD[2] is output 304 * GP61 == LDD[3] is output 305 * GP62 == LDD[4] is output 306 * GP63 == LDD[5] is output 307 * GP64 == LDD[6] is output 308 * GP65 == LDD[7] is output 309 * GP66 == LDD[8] is output 310 * GP67 == LDD[9] is output 311 * GP68 == LDD[10] is output 312 * GP69 == LDD[11] is output 313 * GP70 == LDD[12] is output 314 * GP71 == LDD[13] is output 315 * GP72 == LDD[14] is output 316 * GP73 == LDD[15] is output 317 * GP74 == LCD_FCLK is output 318 * GP75 == LCD_LCLK is output 319 * GP76 == LCD_PCLK is output 320 * GP77 == LCD_ACBIAS is output 321 * GP78 == nCS2 is output 322 * GP79 == nCS3 is output 323 * GP80 == nCS4 is output 324 * GP81 == NSSPCLK is output 325 * GP82 == NSSPSFRM is output 326 * GP83 == NSSPTXD is output 327 * GP84 == NSSPRXD is input 328 */ 329#define CONFIG_SYS_GPDR0_VAL 0xD3E3FC68 330#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB83 331#define CONFIG_SYS_GPDR2_VAL 0x000FFFFF 332 333/* 334 * GP01 == GP reset is AF01 335 * GP15 == nCS1 is AF10 336 * GP16 == PWM0 is AF10 337 * GP17 == PWM1 is AF10 338 * GP18 == RDY is AF01 339 * GP23 == SCLK is AF10 340 * GP24 == SFRM is AF10 341 * GP25 == TXD is AF10 342 * GP26 == RXD is AF01 343 * GP27 == EXTCLK is AF01 344 * GP28 == BITCLK is AF01 345 * GP29 == SDATA_IN0 is AF10 346 * GP30 == SDATA_OUT is AF01 347 * GP31 == SYNC is AF01 348 * GP32 == SYSCLK is AF01 349 * GP33 == nCS5 is AF10 350 * GP34 == FFRXD is AF01 351 * GP35 == CTS is AF01 352 * GP36 == DCD is AF01 353 * GP37 == DSR is AF01 354 * GP38 == RI is AF01 355 * GP39 == FFTXD is AF10 356 * GP40 == DTR is AF10 357 * GP41 == RTS is AF10 358 * GP42 == BTRXD is AF01 359 * GP43 == BTTXD is AF10 360 * GP44 == BTCTS is AF01 361 * GP45 == BTRTS is AF10 362 * GP46 == RXD is AF10 363 * GP47 == TXD is AF01 364 * GP48 == nPOE is AF10 365 * GP49 == nPWE is AF10 366 * GP50 == nPIOR is AF10 367 * GP51 == nPIOW is AF10 368 * GP52 == nPCE[1] is AF10 369 * GP53 == nPCE[2] is AF10 370 * GP54 == nPSKTSEL is AF10 371 * GP55 == nPREG is AF10 372 * GP56 == nPWAIT is AF01 373 * GP57 == nPIOS16 is AF01 374 * GP58 == LDD[0] is AF10 375 * GP59 == LDD[1] is AF10 376 * GP60 == LDD[2] is AF10 377 * GP61 == LDD[3] is AF10 378 * GP62 == LDD[4] is AF10 379 * GP63 == LDD[5] is AF10 380 * GP64 == LDD[6] is AF10 381 * GP65 == LDD[7] is AF10 382 * GP66 == LDD[8] is AF10 383 * GP67 == LDD[9] is AF10 384 * GP68 == LDD[10] is AF10 385 * GP69 == LDD[11] is AF10 386 * GP70 == LDD[12] is AF10 387 * GP71 == LDD[13] is AF10 388 * GP72 == LDD[14] is AF10 389 * GP73 == LDD[15] is AF10 390 * GP74 == LCD_FCLK is AF10 391 * GP75 == LCD_LCLK is AF10 392 * GP76 == LCD_PCLK is AF10 393 * GP77 == LCD_ACBIAS is AF10 394 * GP78 == nCS2 is AF10 395 * GP79 == nCS3 is AF10 396 * GP80 == nCS4 is AF10 397 * GP81 == NSSPCLK is AF01 398 * GP82 == NSSPSFRM is AF01 399 * GP83 == NSSPTXD is AF01 400 * GP84 == NSSPRXD is AF10 401 */ 402#define CONFIG_SYS_GAFR0_L_VAL 0x80000004 403#define CONFIG_SYS_GAFR0_U_VAL 0x595A801A 404#define CONFIG_SYS_GAFR1_L_VAL 0x699A9559 405#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA 406#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA 407#define CONFIG_SYS_GAFR2_U_VAL 0x00000256 408 409/* 410 * clock settings 411 */ 412/* RDH = 1 413 * PH = 0 414 * VFS = 0 415 * BFS = 0 416 * SSS = 0 417 */ 418#define CONFIG_SYS_PSSR_VAL 0x00000030 419 420#define CONFIG_SYS_CKEN 0x00000080 /* */ 421#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ 422#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 423 424 425/* 426 * Memory settings 427 * 428 * This is the configuration for nCS0/1 -> flash banks 429 * configuration for nCS1 : 430 * [31] 0 - 431 * [30:28] 000 - 432 * [27:24] 0000 - 433 * [23:20] 0000 - 434 * [19] 0 - 435 * [18:16] 000 - 436 * configuration for nCS0: 437 * [15] 0 - Slower Device 438 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns 439 * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns 440 * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?) 441 * [03] 0 - 32 Bit bus width 442 * [02:00] 010 - burst OF 4 ROM or FLASH 443*/ 444#define CONFIG_SYS_MSC0_VAL 0x000023D2 445 446/* This is the configuration for nCS2/3 -> USB controller, LAN 447 * configuration for nCS3: LAN 448 * [31] 0 - Slower Device 449 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns 450 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns 451 * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns 452 * [19] 0 - 32 Bit bus width 453 * [18:16] 100 - variable latency I/O 454 * configuration for nCS2: USB 455 * [15] 1 - Faster Device 456 * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns 457 * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns 458 * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns 459 * [03] 1 - 16 Bit bus width 460 * [02:00] 100 - variable latency I/O 461 */ 462#define CONFIG_SYS_MSC1_VAL 0x1224A26C 463 464/* This is the configuration for nCS4/5 -> LAN 465 * configuration for nCS5: 466 * [31] 0 - 467 * [30:28] 000 - 468 * [27:24] 0000 - 469 * [23:20] 0000 - 470 * [19] 0 - 471 * [18:16] 000 - 472 * configuration for nCS4: LAN 473 * [15] 1 - Faster Device 474 * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns 475 * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns 476 * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns 477 * [03] 0 - 32 Bit bus width 478 * [02:00] 100 - variable latency I/O 479 */ 480#define CONFIG_SYS_MSC2_VAL 0x00001224 481 482/* MDCNFG: SDRAM Configuration Register 483 * 484 * [31:29] 000 - reserved 485 * [28] 0 - no SA1111 compatiblity mode 486 * [27] 0 - latch return data with return clock 487 * [26] 0 - alternate addressing for pair 2/3 488 * [25:24] 00 - timings 489 * [23] 0 - internal banks in lower partition 2/3 (not used) 490 * [22:21] 00 - row address bits for partition 2/3 (not used) 491 * [20:19] 00 - column address bits for partition 2/3 (not used) 492 * [18] 0 - SDRAM partition 2/3 width is 32 bit 493 * [17] 0 - SDRAM partition 3 disabled 494 * [16] 0 - SDRAM partition 2 disabled 495 * [15:13] 000 - reserved 496 * [12] 0 - no SA1111 compatiblity mode 497 * [11] 1 - latch return data with return clock 498 * [10] 0 - no alternate addressing for pair 0/1 499 * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk 500 * [7] 1 - 4 internal banks in lower partition pair 501 * [06:05] 10 - 13 row address bits for partition 0/1 502 * [04:03] 01 - 9 column address bits for partition 0/1 503 * [02] 0 - SDRAM partition 0/1 width is 32 bit 504 * [01] 0 - disable SDRAM partition 1 505 * [00] 1 - enable SDRAM partition 0 506 */ 507/* use the configuration above but disable partition 0 */ 508#define CONFIG_SYS_MDCNFG_VAL 0x00000AC9 509 510/* MDREFR: SDRAM Refresh Control Register 511 * 512 * [32:26] 0 - reserved 513 * [25] 0 - K2FREE: not free running 514 * [24] 0 - K1FREE: not free running 515 * [23] 0 - K0FREE: not free running 516 * [22] 0 - SLFRSH: self refresh disabled 517 * [21] 0 - reserved 518 * [20] 1 - APD: auto power down 519 * [19] 0 - K2DB2: SDCLK2 is MemClk 520 * [18] 0 - K2RUN: disable SDCLK2 521 * [17] 0 - K1DB2: SDCLK1 is MemClk 522 * [16] 1 - K1RUN: enable SDCLK1 523 * [15] 1 - E1PIN: SDRAM clock enable 524 * [14] 0 - K0DB2: SDCLK0 is MemClk 525 * [13] 0 - K0RUN: disable SDCLK0 526 * [12] 0 - E0PIN: disable SDCKE0 527 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 528 */ 529#define CONFIG_SYS_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */ 530 531/* MDMRS: Mode Register Set Configuration Register 532 * 533 * [31] 0 - reserved 534 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) 535 * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used) 536 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) 537 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) 538 * [15] 0 - reserved 539 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. 540 * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency. 541 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. 542 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. 543 */ 544#define CONFIG_SYS_MDMRS_VAL 0x00320032 545 546#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 547#define CONFIG_SYS_SXCNFG_VAL 0x00000000 548 549/* 550 * PCMCIA and CF Interfaces 551 */ 552#define CONFIG_SYS_MECR_VAL 0x00000000 553#define CONFIG_SYS_MCMEM0_VAL 0x00010504 554#define CONFIG_SYS_MCMEM1_VAL 0x00010504 555#define CONFIG_SYS_MCATT0_VAL 0x00010504 556#define CONFIG_SYS_MCATT1_VAL 0x00010504 557#define CONFIG_SYS_MCIO0_VAL 0x00004715 558#define CONFIG_SYS_MCIO1_VAL 0x00004715 559 560 561#endif /* __CONFIG_H */ 562