LXR uboot/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c

   1/*
   2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <asm/arch/cpu.h>
   9#include <asm/arch/clk.h>
  10#include <asm/arch/wdt.h>
  11#include <asm/io.h>
  12
  13static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
  14static struct wdt_regs  *wdt = (struct wdt_regs *)WDT_BASE;
  15
  16void reset_cpu(ulong addr)
  17{
  18        /* Enable watchdog clock */
  19        setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
  20
  21        /* Reset pulse length is 13005 peripheral clock frames */
  22        writel(13000, &wdt->pulse);
  23
  24        /* Force WDOG_RESET2 and RESOUT_N signal active */
  25        writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
  26               &wdt->mctrl);
  27
  28        while (1)
  29                /* NOP */;
  30}
  31
  32#if defined(CONFIG_ARCH_CPU_INIT)
  33int arch_cpu_init(void)
  34{
  35        /*
  36         * It might be necessary to flush data cache, if U-boot is loaded
  37         * from kickstart bootloader, e.g. from S1L loader
  38         */
  39        flush_dcache_all();
  40
  41        return 0;
  42}
  43#else
  44#error "You have to select CONFIG_ARCH_CPU_INIT"
  45#endif
  46
  47#if defined(CONFIG_DISPLAY_CPUINFO)
  48int print_cpuinfo(void)
  49{
  50        printf("CPU:   NXP LPC32XX\n");
  51        printf("CPU clock:        %uMHz\n", get_hclk_pll_rate() / 1000000);
  52        printf("AHB bus clock:    %uMHz\n", get_hclk_clk_rate() / 1000000);
  53        printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
  54
  55        return 0;
  56}
  57#endif
  58