1/* 2 * (C) Copyright 2007 3 * 4 * mb86r0x definitions 5 * 6 * Author : Carsten Schneider, mycable GmbH 7 * <cs@mycable.de> 8 * 9 * (C) Copyright 2010 10 * Matthias Weisser <weisserm@arcor.de> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15#ifndef MB86R0X_H 16#define MB86R0X_H 17 18#ifndef __ASSEMBLY__ 19 20/* GPIO registers */ 21struct mb86r0x_gpio { 22 uint32_t gpdr0; 23 uint32_t gpdr1; 24 uint32_t gpdr2; 25 uint32_t res; 26 uint32_t gpddr0; 27 uint32_t gpddr1; 28 uint32_t gpddr2; 29}; 30 31/* PWM registers */ 32struct mb86r0x_pwm { 33 uint32_t bcr; 34 uint32_t tpr; 35 uint32_t pr; 36 uint32_t dr; 37 uint32_t cr; 38 uint32_t sr; 39 uint32_t ccr; 40 uint32_t ir; 41}; 42 43/* The mb86r0x chip control (CCNT) register set. */ 44struct mb86r0x_ccnt { 45 uint32_t ccid; 46 uint32_t csrst; 47 uint32_t pad0[2]; 48 uint32_t cist; 49 uint32_t cistm; 50 uint32_t cgpio_ist; 51 uint32_t cgpio_istm; 52 uint32_t cgpio_ip; 53 uint32_t cgpio_im; 54 uint32_t caxi_bw; 55 uint32_t caxi_ps; 56 uint32_t cmux_md; 57 uint32_t cex_pin_st; 58 uint32_t cmlb; 59 uint32_t pad1[1]; 60 uint32_t cusb; 61 uint32_t pad2[41]; 62 uint32_t cbsc; 63 uint32_t cdcrc; 64 uint32_t cmsr0; 65 uint32_t cmsr1; 66 uint32_t pad3[2]; 67}; 68 69/* The mb86r0x clock reset generator */ 70struct mb86r0x_crg { 71 uint32_t crpr; 72 uint32_t pad0; 73 uint32_t crwr; 74 uint32_t crsr; 75 uint32_t crda; 76 uint32_t crdb; 77 uint32_t crha; 78 uint32_t crpa; 79 uint32_t crpb; 80 uint32_t crhb; 81 uint32_t cram; 82}; 83 84/* The mb86r0x timer */ 85struct mb86r0x_timer { 86 uint32_t load; 87 uint32_t value; 88 uint32_t control; 89 uint32_t intclr; 90 uint32_t ris; 91 uint32_t mis; 92 uint32_t bgload; 93}; 94 95/* mb86r0x gdc display controller */ 96struct mb86r0x_gdc_dsp { 97 /* Display settings */ 98 uint32_t dcm0; 99 uint16_t pad00; 100 uint16_t htp; 101 uint16_t hdp; 102 uint16_t hdb; 103 uint16_t hsp; 104 uint8_t hsw; 105 uint8_t vsw; 106 uint16_t pad01; 107 uint16_t vtr; 108 uint16_t vsp; 109 uint16_t vdp; 110 uint16_t wx; 111 uint16_t wy; 112 uint16_t ww; 113 uint16_t wh; 114 115 /* Layer 0 */ 116 uint32_t l0m; 117 uint32_t l0oa; 118 uint32_t l0da; 119 uint16_t l0dx; 120 uint16_t l0dy; 121 122 /* Layer 1 */ 123 uint32_t l1m; 124 uint32_t cbda0; 125 uint32_t cbda1; 126 uint32_t pad02; 127 128 /* Layer 2 */ 129 uint32_t l2m; 130 uint32_t l2oa0; 131 uint32_t l2da0; 132 uint32_t l2oa1; 133 uint32_t l2da1; 134 uint16_t l2dx; 135 uint16_t l2dy; 136 137 /* Layer 3 */ 138 uint32_t l3m; 139 uint32_t l3oa0; 140 uint32_t l3da0; 141 uint32_t l3oa1; 142 uint32_t l3da1; 143 uint16_t l3dx; 144 uint16_t l3dy; 145 146 /* Layer 4 */ 147 uint32_t l4m; 148 uint32_t l4oa0; 149 uint32_t l4da0; 150 uint32_t l4oa1; 151 uint32_t l4da1; 152 uint16_t l4dx; 153 uint16_t l4dy; 154 155 /* Layer 5 */ 156 uint32_t l5m; 157 uint32_t l5oa0; 158 uint32_t l5da0; 159 uint32_t l5oa1; 160 uint32_t l5da1; 161 uint16_t l5dx; 162 uint16_t l5dy; 163 164 /* Cursor */ 165 uint16_t cutc; 166 uint8_t cpm; 167 uint8_t csize; 168 uint32_t cuoa0; 169 uint16_t cux0; 170 uint16_t cuy0; 171 uint32_t cuoa1; 172 uint16_t cux1; 173 uint16_t cuy1; 174 175 /* Layer blending */ 176 uint32_t l0bld; 177 uint32_t pad03; 178 uint32_t l0tc; 179 uint16_t l3tc; 180 uint16_t l2tc; 181 uint32_t pad04[15]; 182 183 /* Display settings */ 184 uint32_t dcm1; 185 uint32_t dcm2; 186 uint32_t dcm3; 187 uint32_t pad05; 188 189 /* Layer 0 extended */ 190 uint32_t l0em; 191 uint16_t l0wx; 192 uint16_t l0wy; 193 uint16_t l0ww; 194 uint16_t l0wh; 195 uint32_t pad06; 196 197 /* Layer 1 extended */ 198 uint32_t l1em; 199 uint16_t l1wx; 200 uint16_t l1wy; 201 uint16_t l1ww; 202 uint16_t l1wh; 203 uint32_t pad07; 204 205 /* Layer 2 extended */ 206 uint32_t l2em; 207 uint16_t l2wx; 208 uint16_t l2wy; 209 uint16_t l2ww; 210 uint16_t l2wh; 211 uint32_t pad08; 212 213 /* Layer 3 extended */ 214 uint32_t l3em; 215 uint16_t l3wx; 216 uint16_t l3wy; 217 uint16_t l3ww; 218 uint16_t l3wh; 219 uint32_t pad09; 220 221 /* Layer 4 extended */ 222 uint32_t l4em; 223 uint16_t l4wx; 224 uint16_t l4wy; 225 uint16_t l4ww; 226 uint16_t l4wh; 227 uint32_t pad10; 228 229 /* Layer 5 extended */ 230 uint32_t l5em; 231 uint16_t l5wx; 232 uint16_t l5wy; 233 uint16_t l5ww; 234 uint16_t l5wh; 235 uint32_t pad11; 236 237 /* Multi screen control */ 238 uint32_t msc; 239 uint32_t pad12[3]; 240 uint32_t dls; 241 uint32_t dbgc; 242 243 /* Layer blending */ 244 uint32_t l1bld; 245 uint32_t l2bld; 246 uint32_t l3bld; 247 uint32_t l4bld; 248 uint32_t l5bld; 249 uint32_t pad13; 250 251 /* Extended transparency control */ 252 uint32_t l0etc; 253 uint32_t l1etc; 254 uint32_t l2etc; 255 uint32_t l3etc; 256 uint32_t l4etc; 257 uint32_t l5etc; 258 uint32_t pad14[10]; 259 260 /* YUV coefficients */ 261 uint32_t l1ycr0; 262 uint32_t l1ycr1; 263 uint32_t l1ycg0; 264 uint32_t l1ycg1; 265 uint32_t l1ycb0; 266 uint32_t l1ycb1; 267 uint32_t pad15[130]; 268 269 /* Layer palletes */ 270 uint32_t l0pal[256]; 271 uint32_t l1pal[256]; 272 uint32_t pad16[256]; 273 uint32_t l2pal[256]; 274 uint32_t l3pal[256]; 275 uint32_t pad17[256]; 276 277 /* PWM settings */ 278 uint32_t vpwmm; 279 uint16_t vpwms; 280 uint16_t vpwme; 281 uint32_t vpwmc; 282 uint32_t pad18[253]; 283}; 284 285/* mb86r0x gdc capture controller */ 286struct mb86r0x_gdc_cap { 287 uint32_t vcm; 288 uint32_t csc; 289 uint32_t vcs; 290 uint32_t pad01; 291 292 uint32_t cbm; 293 uint32_t cboa; 294 uint32_t cbla; 295 uint16_t cihstr; 296 uint16_t civstr; 297 uint16_t cihend; 298 uint16_t civend; 299 uint32_t pad02; 300 301 uint32_t chp; 302 uint32_t cvp; 303 uint32_t pad03[4]; 304 305 uint32_t clpf; 306 uint32_t pad04; 307 uint32_t cmss; 308 uint32_t cmds; 309 uint32_t pad05[12]; 310 311 uint32_t rgbhc; 312 uint32_t rgbhen; 313 uint32_t rgbven; 314 uint32_t pad06; 315 uint32_t rgbs; 316 uint32_t pad07[11]; 317 318 uint32_t rgbcmy; 319 uint32_t rgbcmcb; 320 uint32_t rgbcmcr; 321 uint32_t rgbcmb; 322 uint32_t pad08[12 + 1984]; 323}; 324 325/* mb86r0x gdc draw */ 326struct mb86r0x_gdc_draw { 327 uint32_t ys; 328 uint32_t xs; 329 uint32_t dxdy; 330 uint32_t xus; 331 uint32_t dxudy; 332 uint32_t xls; 333 uint32_t dxldy; 334 uint32_t usn; 335 uint32_t lsn; 336 uint32_t pad01[7]; 337 uint32_t rs; 338 uint32_t drdx; 339 uint32_t drdy; 340 uint32_t gs; 341 uint32_t dgdx; 342 uint32_t dgdy; 343 uint32_t bs; 344 uint32_t dbdx; 345 uint32_t dbdy; 346 uint32_t pad02[7]; 347 uint32_t zs; 348 uint32_t dzdx; 349 uint32_t dzdy; 350 uint32_t pad03[13]; 351 uint32_t ss; 352 uint32_t dsdx; 353 uint32_t dsdy; 354 uint32_t ts; 355 uint32_t dtdx; 356 uint32_t dtdy; 357 uint32_t qs; 358 uint32_t dqdx; 359 uint32_t dqdy; 360 uint32_t pad04[23]; 361 uint32_t lpn; 362 uint32_t lxs; 363 uint32_t lxde; 364 uint32_t lys; 365 uint32_t lyde; 366 uint32_t lzs; 367 uint32_t lzde; 368 uint32_t pad05[13]; 369 uint32_t pxdc; 370 uint32_t pydc; 371 uint32_t pzdc; 372 uint32_t pad06[25]; 373 uint32_t rxs; 374 uint32_t rys; 375 uint32_t rsizex; 376 uint32_t rsizey; 377 uint32_t pad07[12]; 378 uint32_t saddr; 379 uint32_t sstride; 380 uint32_t srx; 381 uint32_t sry; 382 uint32_t daddr; 383 uint32_t dstride; 384 uint32_t drx; 385 uint32_t dry; 386 uint32_t brsizex; 387 uint32_t brsizey; 388 uint32_t tcolor; 389 uint32_t pad08[93]; 390 uint32_t blpo; 391 uint32_t pad09[7]; 392 uint32_t ctr; 393 uint32_t ifsr; 394 uint32_t ifcnt; 395 uint32_t sst; 396 uint32_t ds; 397 uint32_t pst; 398 uint32_t est; 399 uint32_t pad10; 400 uint32_t mdr0; 401 uint32_t mdr1; 402 uint32_t mdr2; 403 uint32_t mdr3; 404 uint32_t mdr4; 405 uint32_t pad14[2]; 406 uint32_t mdr7; 407 uint32_t fbr; 408 uint32_t xres; 409 uint32_t zbr; 410 uint32_t tbr; 411 uint32_t pfbr; 412 uint32_t cxmin; 413 uint32_t cxmax; 414 uint32_t cymin; 415 uint32_t cymax; 416 uint32_t txs; 417 uint32_t tis; 418 uint32_t toa; 419 uint32_t sho; 420 uint32_t abr; 421 uint32_t pad15[2]; 422 uint32_t fc; 423 uint32_t bc; 424 uint32_t alf; 425 uint32_t blp; 426 uint32_t pad16; 427 uint32_t tbc; 428 uint32_t pad11[42]; 429 uint32_t lx0dc; 430 uint32_t ly0dc; 431 uint32_t lx1dc; 432 uint32_t ly1dc; 433 uint32_t pad12[12]; 434 uint32_t x0dc; 435 uint32_t y0dc; 436 uint32_t x1dc; 437 uint32_t y1dc; 438 uint32_t x2dc; 439 uint32_t y2dc; 440 uint32_t pad13[666]; 441}; 442 443/* mb86r0x gdc geometry engine */ 444struct mb86r0x_gdc_geom { 445 uint32_t gctr; 446 uint32_t pad00[15]; 447 uint32_t gmdr0; 448 uint32_t gmdr1; 449 uint32_t gmdr2; 450 uint32_t pad01[237]; 451 uint32_t dfifog; 452 uint32_t pad02[767]; 453}; 454 455/* mb86r0x gdc */ 456struct mb86r0x_gdc { 457 uint32_t pad00[2]; 458 uint32_t lts; 459 uint32_t pad01; 460 uint32_t lsta; 461 uint32_t pad02[3]; 462 uint32_t ist; 463 uint32_t imask; 464 uint32_t pad03[6]; 465 uint32_t lsa; 466 uint32_t lco; 467 uint32_t lreq; 468 469 uint32_t pad04[16*1024 - 19]; 470 struct mb86r0x_gdc_dsp dsp0; 471 struct mb86r0x_gdc_dsp dsp1; 472 uint32_t pad05[4*1024 - 2]; 473 uint32_t vccc; 474 uint32_t vcsr; 475 struct mb86r0x_gdc_cap cap0; 476 struct mb86r0x_gdc_cap cap1; 477 uint32_t pad06[4*1024]; 478 uint32_t texture_base[16*1024]; 479 struct mb86r0x_gdc_draw draw; 480 uint32_t pad07[7*1024]; 481 struct mb86r0x_gdc_geom geom; 482 uint32_t pad08[7*1024]; 483}; 484 485/* mb86r0x ddr2c */ 486struct mb86r0x_ddr2c { 487 uint16_t dric; 488 uint16_t dric1; 489 uint16_t dric2; 490 uint16_t drca; 491 uint16_t drcm; 492 uint16_t drcst1; 493 uint16_t drcst2; 494 uint16_t drcr; 495 uint16_t pad00[8]; 496 uint16_t drcf; 497 uint16_t pad01[7]; 498 uint16_t drasr; 499 uint16_t pad02[15]; 500 uint16_t drims; 501 uint16_t pad03[7]; 502 uint16_t dros; 503 uint16_t pad04; 504 uint16_t dribsodt1; 505 uint16_t dribsocd; 506 uint16_t dribsocd2; 507 uint16_t pad05[3]; 508 uint16_t droaba; 509 uint16_t pad06[9]; 510 uint16_t drobs; 511 uint16_t pad07[5]; 512 uint16_t drimr1; 513 uint16_t drimr2; 514 uint16_t drimr3; 515 uint16_t drimr4; 516 uint16_t droisr1; 517 uint16_t droisr2; 518}; 519 520/* mb86r0x memc */ 521struct mb86r0x_memc { 522 uint32_t mcfmode[8]; 523 uint32_t mcftim[8]; 524 uint32_t mcfarea[8]; 525}; 526 527#endif /* __ASSEMBLY__ */ 528 529/* 530 * Physical Address Defines 531 */ 532#define MB86R0x_DDR2_BASE 0xf3000000 533#define MB86R0x_GDC_BASE 0xf1fc0000 534#define MB86R0x_CCNT_BASE 0xfff42000 535#define MB86R0x_CAN0_BASE 0xfff54000 536#define MB86R0x_CAN1_BASE 0xfff55000 537#define MB86R0x_I2C0_BASE 0xfff56000 538#define MB86R0x_I2C1_BASE 0xfff57000 539#define MB86R0x_EHCI_BASE 0xfff80000 540#define MB86R0x_OHCI_BASE 0xfff81000 541#define MB86R0x_IRC1_BASE 0xfffb0000 542#define MB86R0x_MEMC_BASE 0xfffc0000 543#define MB86R0x_TIMER_BASE 0xfffe0000 544#define MB86R0x_UART0_BASE 0xfffe1000 545#define MB86R0x_UART1_BASE 0xfffe2000 546#define MB86R0x_IRCE_BASE 0xfffe4000 547#define MB86R0x_CRG_BASE 0xfffe7000 548#define MB86R0x_IRC0_BASE 0xfffe8000 549#define MB86R0x_GPIO_BASE 0xfffe9000 550#define MB86R0x_PWM0_BASE 0xfff41000 551#define MB86R0x_PWM1_BASE 0xfff41100 552 553#define MB86R0x_CRSR_SWRSTREQ (1 << 1) 554 555/* 556 * Timer register bits 557 */ 558#define MB86R0x_TIMER_ENABLE (1 << 7) 559#define MB86R0x_TIMER_MODE_MSK (1 << 6) 560#define MB86R0x_TIMER_MODE_FR (0 << 6) 561#define MB86R0x_TIMER_MODE_PD (1 << 6) 562 563#define MB86R0x_TIMER_INT_EN (1 << 5) 564#define MB86R0x_TIMER_PRS_MSK (3 << 2) 565#define MB86R0x_TIMER_PRS_4S (1 << 2) 566#define MB86R0x_TIMER_PRS_8S (1 << 3) 567#define MB86R0x_TIMER_SIZE_32 (1 << 1) 568#define MB86R0x_TIMER_ONE_SHT (1 << 0) 569 570/* 571 * Clock reset generator bits 572 */ 573#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8) 574#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0) 575#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0) 576#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0) 577#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0) 578#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0) 579#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0) 580#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0) 581#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0) 582#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0) 583#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0) 584#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0) 585#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0) 586#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0) 587/* 588 * DDR2 controller bits 589 */ 590#define MB86R0x_DDR2_DRCI_DRINI (1 << 15) 591#define MB86R0x_DDR2_DRCI_CKEN (1 << 14) 592#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0) 593#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \ 594 MB86R0x_DDR2_DRCI_CKEN | \ 595 MB86R0x_DDR2_DRCI_DRCMD) 596#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \ 597 MB86R0x_DDR2_DRCI_CKEN) 598#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN 599#endif /* MB86R0X_H */ 600