LXR uboot/arch/arm/include/asm/arch-tegra20/usb.h

   1/*
   2 * Copyright (c) 2011 The Chromium OS Authors.
   3 * Copyright (c) 2013 NVIDIA Corporation
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 */
  22
  23#ifndef _TEGRA20_USB_H_
  24#define _TEGRA20_USB_H_
  25
  26/* USB Controller (USBx_CONTROLLER_) regs */
  27struct usb_ctlr {
  28        /* 0x000 */
  29        uint id;
  30        uint reserved0;
  31        uint host;
  32        uint device;
  33
  34        /* 0x010 */
  35        uint txbuf;
  36        uint rxbuf;
  37        uint reserved1[2];
  38
  39        /* 0x020 */
  40        uint reserved2[56];
  41
  42        /* 0x100 */
  43        u16 cap_length;
  44        u16 hci_version;
  45        uint hcs_params;
  46        uint hcc_params;
  47        uint reserved3[5];
  48
  49        /* 0x120 */
  50        uint dci_version;
  51        uint dcc_params;
  52        uint reserved4[6];
  53
  54        /* 0x140 */
  55        uint usb_cmd;
  56        uint usb_sts;
  57        uint usb_intr;
  58        uint frindex;
  59
  60        /* 0x150 */
  61        uint reserved5;
  62        uint periodic_list_base;
  63        uint async_list_addr;
  64        uint async_tt_sts;
  65
  66        /* 0x160 */
  67        uint burst_size;
  68        uint tx_fill_tuning;
  69        uint reserved6;   /* is this port_sc1 on some controllers? */
  70        uint icusb_ctrl;
  71
  72        /* 0x170 */
  73        uint ulpi_viewport;
  74        uint reserved7;
  75        uint endpt_nak;
  76        uint endpt_nak_enable;
  77
  78        /* 0x180 */
  79        uint reserved;
  80        uint port_sc1;
  81        uint reserved8[6];
  82
  83        /* 0x1a0 */
  84        uint reserved9;
  85        uint otgsc;
  86        uint usb_mode;
  87        uint endpt_setup_stat;
  88
  89        /* 0x1b0 */
  90        uint reserved10[20];
  91
  92        /* 0x200 */
  93        uint reserved11[0x80];
  94
  95        /* 0x400 */
  96        uint susp_ctrl;
  97        uint phy_vbus_sensors;
  98        uint phy_vbus_wakeup_id;
  99        uint phy_alt_vbus_sys;
 100
 101        /* 0x410 */
 102        uint usb1_legacy_ctrl;
 103        uint reserved12[4];
 104
 105        /* 0x424 */
 106        uint ulpi_timing_ctrl_0;
 107        uint ulpi_timing_ctrl_1;
 108        uint reserved13[53];
 109
 110        /* 0x500 */
 111        uint reserved14[64 * 3];
 112
 113        /* 0x800 */
 114        uint utmip_pll_cfg0;
 115        uint utmip_pll_cfg1;
 116        uint utmip_xcvr_cfg0;
 117        uint utmip_bias_cfg0;
 118
 119        /* 0x810 */
 120        uint utmip_hsrx_cfg0;
 121        uint utmip_hsrx_cfg1;
 122        uint utmip_fslsrx_cfg0;
 123        uint utmip_fslsrx_cfg1;
 124
 125        /* 0x820 */
 126        uint utmip_tx_cfg0;
 127        uint utmip_misc_cfg0;
 128        uint utmip_misc_cfg1;
 129        uint utmip_debounce_cfg0;
 130
 131        /* 0x830 */
 132        uint utmip_bat_chrg_cfg0;
 133        uint utmip_spare_cfg0;
 134        uint utmip_xcvr_cfg1;
 135        uint utmip_bias_cfg1;
 136};
 137
 138/* USB2_IF_ULPI_TIMING_CTRL_0 */
 139#define ULPI_OUTPUT_PINMUX_BYP                  (1 << 10)
 140#define ULPI_CLKOUT_PINMUX_BYP                  (1 << 11)
 141
 142/* USB2_IF_ULPI_TIMING_CTRL_1 */
 143#define ULPI_DATA_TRIMMER_LOAD                  (1 << 0)
 144#define ULPI_DATA_TRIMMER_SEL(x)                (((x) & 0x7) << 1)
 145#define ULPI_STPDIRNXT_TRIMMER_LOAD             (1 << 16)
 146#define ULPI_STPDIRNXT_TRIMMER_SEL(x)   (((x) & 0x7) << 17)
 147#define ULPI_DIR_TRIMMER_LOAD                   (1 << 24)
 148#define ULPI_DIR_TRIMMER_SEL(x)                 (((x) & 0x7) << 25)
 149
 150/* PORTSC, USB2, USB3 */
 151#define PTS_SHIFT               30
 152#define PTS_MASK                (3U << PTS_SHIFT)
 153
 154#define STS                     (1 << 29)
 155#endif /* _TEGRA20_USB_H_ */
 156