1/* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2013 NVIDIA Corporation 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23#ifndef _TEGRA30_USB_H_ 24#define _TEGRA30_USB_H_ 25 26/* USB Controller (USBx_CONTROLLER_) regs */ 27struct usb_ctlr { 28 /* 0x000 */ 29 uint id; 30 uint reserved0; 31 uint host; 32 uint device; 33 34 /* 0x010 */ 35 uint txbuf; 36 uint rxbuf; 37 uint reserved1[2]; 38 39 /* 0x020 */ 40 uint reserved2[56]; 41 42 /* 0x100 */ 43 u16 cap_length; 44 u16 hci_version; 45 uint hcs_params; 46 uint hcc_params; 47 uint reserved3[5]; 48 49 /* 0x120 */ 50 uint dci_version; 51 uint dcc_params; 52 uint reserved4[2]; 53 54 /* 0x130 */ 55 uint usb_cmd; 56 uint usb_sts; 57 uint usb_intr; 58 uint frindex; 59 60 /* 0x140 */ 61 uint reserved5; 62 uint periodic_list_base; 63 uint async_list_addr; 64 uint reserved5_1; 65 66 /* 0x150 */ 67 uint burst_size; 68 uint tx_fill_tuning; 69 uint reserved6; 70 uint icusb_ctrl; 71 72 /* 0x160 */ 73 uint ulpi_viewport; 74 uint reserved7[3]; 75 76 /* 0x170 */ 77 uint reserved; 78 uint port_sc1; 79 uint reserved8[6]; 80 81 /* 0x190 */ 82 uint reserved9[8]; 83 84 /* 0x1b0 */ 85 uint reserved10; 86 uint hostpc1_devlc; 87 uint reserved10_1[2]; 88 89 /* 0x1c0 */ 90 uint reserved10_2[4]; 91 92 /* 0x1d0 */ 93 uint reserved10_3[4]; 94 95 /* 0x1e0 */ 96 uint reserved10_4[4]; 97 98 /* 0x1f0 */ 99 uint reserved10_5; 100 uint otgsc; 101 uint usb_mode; 102 uint reserved10_6; 103 104 /* 0x200 */ 105 uint endpt_nak; 106 uint endpt_nak_enable; 107 uint endpt_setup_stat; 108 uint reserved11_1[0x7D]; 109 110 /* 0x400 */ 111 uint susp_ctrl; 112 uint phy_vbus_sensors; 113 uint phy_vbus_wakeup_id; 114 uint phy_alt_vbus_sys; 115 116 /* 0x410 */ 117 uint usb1_legacy_ctrl; 118 uint reserved12[3]; 119 120 /* 0x420 */ 121 uint reserved13[56]; 122 123 /* 0x500 */ 124 uint reserved14[64 * 3]; 125 126 /* 0x800 */ 127 uint utmip_pll_cfg0; 128 uint utmip_pll_cfg1; 129 uint utmip_xcvr_cfg0; 130 uint utmip_bias_cfg0; 131 132 /* 0x810 */ 133 uint utmip_hsrx_cfg0; 134 uint utmip_hsrx_cfg1; 135 uint utmip_fslsrx_cfg0; 136 uint utmip_fslsrx_cfg1; 137 138 /* 0x820 */ 139 uint utmip_tx_cfg0; 140 uint utmip_misc_cfg0; 141 uint utmip_misc_cfg1; 142 uint utmip_debounce_cfg0; 143 144 /* 0x830 */ 145 uint utmip_bat_chrg_cfg0; 146 uint utmip_spare_cfg0; 147 uint utmip_xcvr_cfg1; 148 uint utmip_bias_cfg1; 149}; 150 151/* USB2_IF_ULPI_TIMING_CTRL_0 */ 152#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) 153#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) 154 155/* USB2_IF_ULPI_TIMING_CTRL_1 */ 156#define ULPI_DATA_TRIMMER_LOAD (1 << 0) 157#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) 158#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) 159#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) 160#define ULPI_DIR_TRIMMER_LOAD (1 << 24) 161#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) 162 163/* USB2D_HOSTPC1_DEVLC_0 */ 164#define PTS_SHIFT 29 165#define PTS_MASK (0x7U << PTS_SHIFT) 166 167#define STS (1 << 28) 168#endif /* _TEGRA30_USB_H_ */ 169