LXR uboot/arch/blackfin/lib/clocks.c

   1/*
   2 * clocks.c - figure out sclk/cclk/vco and such
   3 *
   4 * Copyright (c) 2005-2008 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2 or later.
   7 */
   8
   9#include <common.h>
  10#include <asm/clock.h>
  11
  12/* Get the voltage input multiplier */
  13u_long get_vco(void)
  14{
  15        static u_long cached_vco_pll_ctl, cached_vco;
  16
  17        u_long msel, pll_ctl;
  18
  19        pll_ctl = bfin_read_PLL_CTL();
  20        if (pll_ctl == cached_vco_pll_ctl)
  21                return cached_vco;
  22        else
  23                cached_vco_pll_ctl = pll_ctl;
  24
  25        msel = (pll_ctl & MSEL) >> MSEL_P;
  26        if (0 == msel)
  27                msel = (MSEL >> MSEL_P) + 1;
  28
  29        cached_vco = CONFIG_CLKIN_HZ;
  30        cached_vco >>= (pll_ctl & DF);
  31        cached_vco *= msel;
  32        return cached_vco;
  33}
  34
  35/* Get the Core clock */
  36u_long get_cclk(void)
  37{
  38        static u_long cached_cclk_pll_div, cached_cclk;
  39        u_long div, csel, ssel;
  40
  41        if (pll_is_bypassed())
  42                return CONFIG_CLKIN_HZ;
  43
  44        div = bfin_read_PLL_DIV();
  45        if (div == cached_cclk_pll_div)
  46                return cached_cclk;
  47        else
  48                cached_cclk_pll_div = div;
  49
  50        csel = (div & CSEL) >> CSEL_P;
  51#ifndef CGU_DIV
  52        ssel = (div & SSEL) >> SSEL_P;
  53        if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
  54                cached_cclk = get_vco() / ssel;
  55        else
  56                cached_cclk = get_vco() >> csel;
  57#else
  58        cached_cclk = get_vco() / csel;
  59#endif
  60        return cached_cclk;
  61}
  62
  63/* Get the System clock */
  64#ifdef CGU_DIV
  65
  66static u_long cached_sclk_pll_div, cached_sclk;
  67static u_long cached_sclk0, cached_sclk1, cached_dclk;
  68static u_long _get_sclk(u_long *cache)
  69{
  70        u_long div, ssel;
  71
  72        if (pll_is_bypassed())
  73                return CONFIG_CLKIN_HZ;
  74
  75        div = bfin_read_PLL_DIV();
  76        if (div == cached_sclk_pll_div)
  77                return *cache;
  78        else
  79                cached_sclk_pll_div = div;
  80
  81        ssel = (div & SYSSEL) >> SYSSEL_P;
  82        cached_sclk = get_vco() / ssel;
  83
  84        ssel = (div & S0SEL) >> S0SEL_P;
  85        cached_sclk0 = cached_sclk / ssel;
  86
  87        ssel = (div & S1SEL) >> S1SEL_P;
  88        cached_sclk1 = cached_sclk / ssel;
  89
  90        ssel = (div & DSEL) >> DSEL_P;
  91        cached_dclk = get_vco() / ssel;
  92
  93        return *cache;
  94}
  95
  96u_long get_sclk(void)
  97{
  98        return _get_sclk(&cached_sclk);
  99}
 100
 101u_long get_sclk0(void)
 102{
 103        return _get_sclk(&cached_sclk0);
 104}
 105
 106u_long get_sclk1(void)
 107{
 108        return _get_sclk(&cached_sclk1);
 109}
 110
 111u_long get_dclk(void)
 112{
 113        return _get_sclk(&cached_dclk);
 114}
 115#else
 116
 117u_long get_sclk(void)
 118{
 119        static u_long cached_sclk_pll_div, cached_sclk;
 120        u_long div, ssel;
 121
 122        if (pll_is_bypassed())
 123                return CONFIG_CLKIN_HZ;
 124
 125        div = bfin_read_PLL_DIV();
 126        if (div == cached_sclk_pll_div)
 127                return cached_sclk;
 128        else
 129                cached_sclk_pll_div = div;
 130
 131        ssel = (div & SSEL) >> SSEL_P;
 132        cached_sclk = get_vco() / ssel;
 133
 134        return cached_sclk;
 135}
 136
 137#endif
 138