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15#include <common.h>
16#include <fdt_support.h>
17#include <i2c.h>
18#include <libfdt.h>
19#include <asm/ppc440.h>
20#include <asm/bitops.h>
21#include <asm/ppc4xx-gpio.h>
22#include <asm/io.h>
23#include <asm/ppc4xx-uic.h>
24#include <asm/processor.h>
25#include <asm/4xx_pci.h>
26
27DECLARE_GLOBAL_DATA_PTR;
28
29extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
30
31ulong flash_get_size(ulong base, int banknum);
32
33#if defined(CONFIG_KORAT_PERMANENT)
34void korat_buzzer(int const on)
35{
36 if (on) {
37 out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
38 in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80);
39 } else {
40 out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
41 in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80);
42 }
43}
44#endif
45
46int board_early_init_f(void)
47{
48 uint32_t sdr0_pfc1, sdr0_pfc2;
49 uint32_t reg;
50 int eth;
51
52#if defined(CONFIG_KORAT_PERMANENT)
53 unsigned mscount;
54
55 extern void korat_branch_absolute(uint32_t addr);
56
57 for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) {
58 udelay(1000);
59 if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) {
60
61 korat_branch_absolute(
62 CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4);
63 }
64 }
65 korat_buzzer(1);
66 while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_))
67 udelay(1000);
68
69 korat_buzzer(0);
70#endif
71
72 mtdcr(EBC0_CFGADDR, EBC0_CFG);
73 mtdcr(EBC0_CFGDATA, 0xb8400000);
74
75
76
77
78 mtdcr(UIC0SR, 0xffffffff);
79 mtdcr(UIC0ER, 0x00000000);
80 mtdcr(UIC0CR, 0x00000005);
81 mtdcr(UIC0PR, 0xfffff7ff);
82 mtdcr(UIC0TR, 0x00000000);
83 mtdcr(UIC0VR, 0x00000000);
84 mtdcr(UIC0SR, 0xffffffff);
85
86 mtdcr(UIC1SR, 0xffffffff);
87 mtdcr(UIC1ER, 0x00000000);
88 mtdcr(UIC1CR, 0x00000000);
89 mtdcr(UIC1PR, 0xffffffff);
90 mtdcr(UIC1TR, 0x00000000);
91 mtdcr(UIC1VR, 0x00000000);
92 mtdcr(UIC1SR, 0xffffffff);
93
94 mtdcr(UIC2SR, 0xffffffff);
95 mtdcr(UIC2ER, 0x00000000);
96 mtdcr(UIC2CR, 0x00000000);
97 mtdcr(UIC2PR, 0xffffffff);
98 mtdcr(UIC2TR, 0x00000000);
99 mtdcr(UIC2VR, 0x00000000);
100 mtdcr(UIC2SR, 0xffffffff);
101
102
103
104
105
106 out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0);
107
108
109
110
111 for (eth = 0; eth < 2; ++eth) {
112 if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) {
113
114
115 out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
116 in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) |
117 0x06 << (4 * eth));
118 } else {
119
120
121 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1);
122 gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0);
123 }
124 }
125
126 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1);
127 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1);
128
129
130 udelay(1000);
131 out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
132 in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88);
133
134
135 mfsdr(SDR0_PFC1, sdr0_pfc1);
136 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
137 SDR0_PFC1_SELECT_CONFIG_4;
138#ifdef CONFIG_I2C_MULTI_BUS
139 sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
140#endif
141 mfsdr(SDR0_PFC2, sdr0_pfc2);
142 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
143 SDR0_PFC2_SELECT_CONFIG_4;
144 mtsdr(SDR0_PFC2, sdr0_pfc2);
145 mtsdr(SDR0_PFC1, sdr0_pfc1);
146
147
148 mfsdr(SDR0_PCI0, reg);
149 mtsdr(SDR0_PCI0, 0x80000000 | reg);
150
151 return 0;
152}
153
154
155
156
157
158
159ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
160{
161 uint32_t addr;
162 int i;
163
164 if (1 != banknum)
165 return 0;
166
167 info->size = CONFIG_SYS_FLASH0_SIZE;
168 info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000;
169 info->flash_id = 0x01000000;
170 info->portwidth = 2;
171 info->chipwidth = 2;
172 info->buffer_size = 32;
173 info->erase_blk_tout = 16384;
174 info->write_tout = 2;
175 info->buffer_write_tout = 5;
176 info->vendor = 2;
177 info->cmd_reset = 0x00F0;
178 info->interface = 2;
179 info->legacy_unlock = 0;
180 info->manufacturer_id = 1;
181 info->device_id = 0x007E;
182
183#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
184 info->device_id2 = 0x2101;
185#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
186 info->device_id2 = 0x2301;
187#else
188#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE
189#endif
190
191 info->ext_addr = 0x0040;
192 info->cfi_version = 0x3133;
193 info->cfi_offset = 0x0055;
194 info->addr_unlock1 = 0x00000555;
195 info->addr_unlock2 = 0x000002AA;
196 info->name = "CFI conformant";
197 for (i = 0, addr = -info->size;
198 i < info->sector_count;
199 ++i, addr += 0x20000) {
200 info->start[i] = addr;
201 info->protect[i] = 0x00;
202 }
203 return 1;
204}
205
206static int man_data_read(unsigned int addr)
207{
208
209
210
211
212 u8 data[2];
213
214 if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
215 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
216 debug("man_data_read(0x%02X) failed\n", addr);
217 return -1;
218 }
219 debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
220 return data[0];
221}
222
223static unsigned int man_data_field_addr(unsigned int const field)
224{
225
226
227
228
229
230 unsigned addr, i;
231
232 if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
233
234 return 0;
235
236 for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
237 if ('\0' == man_data_read(addr))
238 ++i;
239 }
240 return (addr < 256) ? addr : 0;
241}
242
243static char *man_data_read_field(char s[], unsigned const field,
244 unsigned const length)
245{
246
247
248
249
250
251
252 unsigned addr, i;
253
254 addr = man_data_field_addr(field);
255 if (0 == addr || addr + length >= 255)
256 return 0;
257
258 for (i = 0; i < length; ++i) {
259 int const c = man_data_read(addr++);
260
261 if (c <= 0)
262 return 0;
263
264 s[i] = (char)c;
265 }
266 if (0 != man_data_read(addr))
267 return 0;
268
269 s[i] = '\0';
270 return s;
271}
272
273static void set_serial_number(void)
274{
275
276
277
278
279 char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
280
281 if (getenv("serial#"))
282 return;
283
284 if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
285 return;
286
287 s[MAN_INFO_LENGTH] = '-';
288 if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
289 MAN_MAC_ADDR_LENGTH))
290 return;
291
292 setenv("serial#", s);
293}
294
295static void set_mac_addresses(void)
296{
297
298
299
300
301
302
303#if MAN_MAC_ADDR_LENGTH % 2 != 0
304#error MAN_MAC_ADDR_LENGTH must be an even number
305#endif
306
307 char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
308 char *src;
309 char *dst;
310
311 if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
312 return;
313
314 if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
315 MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
316 return;
317
318 for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
319 *dst++ = *src++;
320 *dst++ = *src++;
321 *dst++ = ':';
322 }
323 if (0 == getenv("ethaddr"))
324 setenv("ethaddr", s);
325
326 if (0 == getenv("eth1addr")) {
327 ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
328 setenv("eth1addr", s);
329 }
330}
331
332int misc_init_r(void)
333{
334 uint32_t pbcr;
335 int size_val;
336 uint32_t reg;
337 unsigned long usb2d0cr = 0;
338 unsigned long usb2phy0cr, usb2h0cr = 0;
339 unsigned long sdr0_pfc1;
340 uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
341 char const *const act = getenv("usbact");
342 char const *const usbcf = getenv("korat_usbcf");
343
344
345
346
347 gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size;
348 gd->bd->bi_flashoffset = 0;
349
350 mtdcr(EBC0_CFGADDR, PB1CR);
351 pbcr = mfdcr(EBC0_CFGDATA);
352 size_val = ffs(flash1_size) - 21;
353 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
354 mtdcr(EBC0_CFGADDR, PB1CR);
355 mtdcr(EBC0_CFGDATA, pbcr);
356
357
358
359
360 flash_get_size(gd->bd->bi_flashstart, 0);
361
362
363
364
365
366 gd->bd->bi_flashoffset =
367 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR;
368
369 mtdcr(EBC0_CFGADDR, PB1CR);
370 pbcr = mfdcr(EBC0_CFGDATA);
371 size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21;
372 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
373 mtdcr(EBC0_CFGADDR, PB1CR);
374 mtdcr(EBC0_CFGDATA, pbcr);
375
376
377#if defined(CONFIG_KORAT_PERMANENT)
378 (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
379 CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
380 flash_info + 1);
381#else
382 (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
383 CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
384 flash_info);
385#endif
386
387 (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
388 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
389 flash_info);
390 (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
391 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
392 flash_info);
393
394
395
396
397
398
399
400
401 if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) {
402
403
404
405
406
407 printf("Attaching CompactFlash controller to PPC USB\n");
408 out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
409 in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
410 } else {
411 if (usbcf != NULL && (strcmp(usbcf, "pci") != 0))
412 printf("Warning: \"korat_usbcf\" is not set to a legal "
413 "value (\"ppc\" or \"pci\")\n");
414
415 printf("Attaching CompactFlash controller to PCI USB\n");
416 }
417 if (act == NULL || strcmp(act, "hostdev") == 0) {
418
419 mfsdr(SDR0_PFC1, sdr0_pfc1);
420 mfsdr(SDR0_USB2D0CR, usb2d0cr);
421 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
422 mfsdr(SDR0_USB2H0CR, usb2h0cr);
423
424 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
425 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
426 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
427 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
428 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
429 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
430 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
431 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
432 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
433 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
434
435
436
437
438
439 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
440 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
441
442
443
444
445
446 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
447 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
448
449 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
450 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
451
452 mtsdr(SDR0_PFC1, sdr0_pfc1);
453 mtsdr(SDR0_USB2D0CR, usb2d0cr);
454 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
455 mtsdr(SDR0_USB2H0CR, usb2h0cr);
456
457
458 udelay(1000);
459 mtsdr(SDR0_SRST1, 0x00000000);
460 udelay(1000);
461 mtsdr(SDR0_SRST0, 0x00000000);
462
463 printf("USB: Host(int phy) Device(ext phy)\n");
464
465 } else if (strcmp(act, "dev") == 0) {
466
467 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
468
469 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
470 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
471 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
472 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
473 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
474 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
475 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
476 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
477 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
478
479 udelay(1000);
480 mtsdr(SDR0_SRST1, 0x672c6000);
481
482 udelay(1000);
483 mtsdr(SDR0_SRST0, 0x00000080);
484
485 udelay(1000);
486 mtsdr(SDR0_SRST1, 0x60206000);
487
488 *(unsigned int *)(0xe0000350) = 0x00000001;
489
490 udelay(1000);
491 mtsdr(SDR0_SRST1, 0x60306000);
492
493
494
495 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
496 mfsdr(SDR0_USB2H0CR, usb2h0cr);
497 mfsdr(SDR0_USB2D0CR, usb2d0cr);
498 mfsdr(SDR0_PFC1, sdr0_pfc1);
499
500 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
501 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
502 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
503 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
504 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
505 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
506 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
507 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
508 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
509 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
510
511 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
512 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
513
514 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
515 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
516
517 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
518 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
519
520 mtsdr(SDR0_USB2H0CR, usb2h0cr);
521 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
522 mtsdr(SDR0_USB2D0CR, usb2d0cr);
523 mtsdr(SDR0_PFC1, sdr0_pfc1);
524
525
526 udelay(1000);
527 mtsdr(SDR0_SRST1, 0x00000000);
528 udelay(1000);
529 mtsdr(SDR0_SRST0, 0x00000000);
530
531 printf("USB: Device(int phy)\n");
532 }
533
534 mfsdr(SDR0_SRST1, reg);
535 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
536 mtsdr(SDR0_SRST1, reg);
537
538
539
540
541
542
543 reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
544 mtdcr(PLB4A0_ACR, reg);
545
546 set_serial_number();
547 set_mac_addresses();
548 gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1);
549
550 return 0;
551}
552
553int checkboard(void)
554{
555 char const *const s = getenv("serial#");
556 u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0);
557
558 printf("Board: Korat, Rev. %X", rev);
559 if (s)
560 printf(", serial# %s", s);
561
562 printf(".\n Ethernet PHY 0: ");
563 if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL))
564 printf("fiber");
565 else
566 printf("copper");
567
568 printf(", PHY 1: ");
569 if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL))
570 printf("fiber");
571 else
572 printf("copper");
573
574 printf(".\n");
575#if defined(CONFIG_KORAT_PERMANENT)
576 printf(" Executing permanent copy of U-Boot.\n");
577#endif
578 return 0;
579}
580
581#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
582
583
584
585void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
586{
587 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
588}
589#endif
590
591
592
593
594
595
596
597
598#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
599void pci_target_init(struct pci_controller *hose)
600{
601
602 __pci_target_init(hose);
603
604
605
606
607
608 pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
609}
610#endif
611
612#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
613void ft_board_setup(void *blob, bd_t *bd)
614{
615 u32 val[4];
616 int rc;
617
618 ft_cpu_setup(blob, bd);
619
620
621 val[0] = 1;
622 val[1] = 0;
623 val[2] = gd->bd->bi_flashstart;
624 val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
625 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
626 val, sizeof(val), 1);
627 if (rc)
628 printf("Unable to update property NOR mapping, err=%s\n",
629 fdt_strerror(rc));
630}
631#endif
632