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9#include <common.h>
10#include <ioports.h>
11#include <mpc8260.h>
12#include <asm/cpm_8260.h>
13#include <configs/sacsng.h>
14
15#include "clkinit.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
19int Daq64xSampling = 0;
20
21
22void Daq_BRG_Reset(uint brg)
23{
24 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
25 volatile uint *brg_ptr;
26
27 brg_ptr = (uint *)&immr->im_brgc1;
28
29 if (brg >= 5) {
30 brg_ptr = (uint *)&immr->im_brgc5;
31 brg -= 4;
32 }
33 brg_ptr += brg;
34 *brg_ptr |= CPM_BRG_RST;
35 *brg_ptr &= ~CPM_BRG_RST;
36}
37
38void Daq_BRG_Disable(uint brg)
39{
40 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
41 volatile uint *brg_ptr;
42
43 brg_ptr = (uint *)&immr->im_brgc1;
44
45 if (brg >= 5) {
46 brg_ptr = (uint *)&immr->im_brgc5;
47 brg -= 4;
48 }
49 brg_ptr += brg;
50 *brg_ptr &= ~CPM_BRG_EN;
51}
52
53void Daq_BRG_Enable(uint brg)
54{
55 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
56 volatile uint *brg_ptr;
57
58 brg_ptr = (uint *)&immr->im_brgc1;
59 if (brg >= 5) {
60 brg_ptr = (uint *)&immr->im_brgc5;
61 brg -= 4;
62 }
63 brg_ptr += brg;
64 *brg_ptr |= CPM_BRG_EN;
65}
66
67uint Daq_BRG_Get_Div16(uint brg)
68{
69 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
70 uint *brg_ptr;
71
72 brg_ptr = (uint *)&immr->im_brgc1;
73 if (brg >= 5) {
74 brg_ptr = (uint *)&immr->im_brgc5;
75 brg -= 4;
76 }
77 brg_ptr += brg;
78
79 if (*brg_ptr & CPM_BRG_DIV16) {
80
81 return true;
82 }
83 else {
84
85 return false;
86 }
87}
88
89void Daq_BRG_Set_Div16(uint brg, uint div16)
90{
91 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
92 uint *brg_ptr;
93
94 brg_ptr = (uint *)&immr->im_brgc1;
95 if (brg >= 5) {
96 brg_ptr = (uint *)&immr->im_brgc5;
97 brg -= 4;
98 }
99 brg_ptr += brg;
100
101 if (div16) {
102
103 *brg_ptr |= CPM_BRG_DIV16;
104 }
105 else {
106
107 *brg_ptr &= ~CPM_BRG_DIV16;
108 }
109}
110
111uint Daq_BRG_Get_Count(uint brg)
112{
113 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
114 uint *brg_ptr;
115 uint brg_cnt;
116
117 brg_ptr = (uint *)&immr->im_brgc1;
118 if (brg >= 5) {
119 brg_ptr = (uint *)&immr->im_brgc5;
120 brg -= 4;
121 }
122 brg_ptr += brg;
123
124
125
126
127
128
129 brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
130 brg_cnt++;
131 if (*brg_ptr & CPM_BRG_DIV16) {
132 brg_cnt *= 16;
133 }
134
135 return (brg_cnt);
136}
137
138void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
139{
140 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
141 uint *brg_ptr;
142
143 brg_ptr = (uint *)&immr->im_brgc1;
144 if (brg >= 5) {
145 brg_ptr = (uint *)&immr->im_brgc5;
146 brg -= 4;
147 }
148 brg_ptr += brg;
149
150
151
152
153
154 if (brg_cnt > 4096) {
155
156 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
157 (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
158 *brg_ptr |= CPM_BRG_DIV16;
159 }
160 else {
161
162 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
163 ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
164 *brg_ptr &= ~CPM_BRG_DIV16;
165 }
166}
167
168uint Daq_BRG_Get_ExtClk(uint brg)
169{
170 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
171 uint *brg_ptr;
172
173 brg_ptr = (uint *)&immr->im_brgc1;
174 if (brg >= 5) {
175 brg_ptr = (uint *)&immr->im_brgc5;
176 brg -= 4;
177 }
178 brg_ptr += brg;
179
180 return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
181}
182
183char* Daq_BRG_Get_ExtClk_Description(uint brg)
184{
185 uint extc;
186
187 extc = Daq_BRG_Get_ExtClk(brg);
188
189 switch (brg + 1) {
190 case 1:
191 case 2:
192 case 5:
193 case 6: {
194 switch (extc) {
195 case 0: {
196 return ("BRG_INT");
197 }
198 case 1: {
199 return ("CLK3");
200 }
201 case 2: {
202 return ("CLK5");
203 }
204 }
205 return ("??1245??");
206 }
207 case 3:
208 case 4:
209 case 7:
210 case 8: {
211 switch (extc) {
212 case 0: {
213 return ("BRG_INT");
214 }
215 case 1: {
216 return ("CLK9");
217 }
218 case 2: {
219 return ("CLK15");
220 }
221 }
222 return ("??3478??");
223 }
224 }
225 return ("??9876??");
226}
227
228void Daq_BRG_Set_ExtClk(uint brg, uint extc)
229{
230 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
231 uint *brg_ptr;
232
233 brg_ptr = (uint *)&immr->im_brgc1;
234 if (brg >= 5) {
235 brg_ptr = (uint *)&immr->im_brgc5;
236 brg -= 4;
237 }
238 brg_ptr += brg;
239
240 *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
241 ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
242}
243
244uint Daq_BRG_Rate(uint brg)
245{
246 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
247 uint *brg_ptr;
248 uint brg_cnt;
249 uint brg_freq = 0;
250
251 brg_ptr = (uint *)&immr->im_brgc1;
252 brg_ptr += brg;
253 if (brg >= 5) {
254 brg_ptr = (uint *)&immr->im_brgc5;
255 brg_ptr += (brg - 4);
256 }
257
258 brg_cnt = Daq_BRG_Get_Count(brg);
259
260 switch (Daq_BRG_Get_ExtClk(brg)) {
261 case CPM_BRG_EXTC_CLK3:
262 case CPM_BRG_EXTC_CLK5: {
263 brg_freq = brg_cnt;
264 break;
265 }
266 default: {
267 brg_freq = (uint)BRG_INT_CLK / brg_cnt;
268 }
269 }
270 return (brg_freq);
271}
272
273uint Daq_Get_SampleRate(void)
274{
275
276
277
278 return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
279}
280
281void Daq_Init_Clocks(int sample_rate, int sample_64x)
282{
283 volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 );
284 uint mclk_divisor;
285 int flag;
286
287
288 Daq64xSampling = sample_64x;
289
290
291
292
293 if (sample_rate > MAX_64x_SAMPLE_RATE) {
294 sample_rate = MAX_64x_SAMPLE_RATE;
295 }
296 if (sample_rate < MIN_SAMPLE_RATE) {
297 sample_rate = MIN_SAMPLE_RATE;
298 }
299
300
301
302
303
304
305 Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
306
307
308# ifdef RUN_SCLK_ON_BRG_INT
309 Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
310# else
311 Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
312# endif
313
314
315# ifdef RUN_LRCLK_ON_BRG_INT
316 Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
317# else
318 Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
319# endif
320
321
322
323
324
325
326 mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
327
328
329
330
331 flag = disable_interrupts();
332
333
334 Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
335
336
337# ifdef RUN_SCLK_ON_BRG_INT
338 Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
339# else
340 Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
341# endif
342
343# ifdef RUN_LRCLK_ON_BRG_INT
344 Daq_BRG_Set_Count(LRCLK_BRG,
345 mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
346# else
347 Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
348# endif
349
350
351
352
353 if (flag) {
354 enable_interrupts();
355 }
356
357
358 iopa->pdat &= ~SLRCLK_EN_MASK;
359}
360
361void Daq_Stop_Clocks(void)
362
363{
364#ifdef TIGHTEN_UP_BRG_TIMING
365 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
366 register uint mclk_brg;
367 register uint sclk_brg;
368 register uint lrclk_brg;
369 unsigned long flag;
370#endif
371
372# ifdef TIGHTEN_UP_BRG_TIMING
373
374
375
376# if (MCLK_BRG == 0)
377 mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
378# endif
379# if (MCLK_BRG == 1)
380 mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
381# endif
382# if (MCLK_BRG == 2)
383 mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
384# endif
385# if (MCLK_BRG == 3)
386 mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
387# endif
388# if (MCLK_BRG == 4)
389 mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
390# endif
391# if (MCLK_BRG == 5)
392 mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
393# endif
394# if (MCLK_BRG == 6)
395 mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
396# endif
397# if (MCLK_BRG == 7)
398 mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
399# endif
400
401
402
403
404# if (SCLK_BRG == 0)
405 sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
406# endif
407# if (SCLK_BRG == 1)
408 sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
409# endif
410# if (SCLK_BRG == 2)
411 sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
412# endif
413# if (SCLK_BRG == 3)
414 sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
415# endif
416# if (SCLK_BRG == 4)
417 sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
418# endif
419# if (SCLK_BRG == 5)
420 sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
421# endif
422# if (SCLK_BRG == 6)
423 sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
424# endif
425# if (SCLK_BRG == 7)
426 sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
427# endif
428
429
430
431
432# if (LRCLK_BRG == 0)
433 lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
434# endif
435# if (LRCLK_BRG == 1)
436 lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
437# endif
438# if (LRCLK_BRG == 2)
439 lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
440# endif
441# if (LRCLK_BRG == 3)
442 lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
443# endif
444# if (LRCLK_BRG == 4)
445 lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
446# endif
447# if (LRCLK_BRG == 5)
448 lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
449# endif
450# if (LRCLK_BRG == 6)
451 lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
452# endif
453# if (LRCLK_BRG == 7)
454 lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
455# endif
456
457
458
459
460 flag = disable_interrupts();
461
462
463
464
465# if (MCLK_BRG == 0)
466 *IM_BRGC1 = mclk_brg;
467# endif
468# if (MCLK_BRG == 1)
469 *IM_BRGC2 = mclk_brg;
470# endif
471# if (MCLK_BRG == 2)
472 *IM_BRGC3 = mclk_brg;
473# endif
474# if (MCLK_BRG == 3)
475 *IM_BRGC4 = mclk_brg;
476# endif
477# if (MCLK_BRG == 4)
478 *IM_BRGC5 = mclk_brg;
479# endif
480# if (MCLK_BRG == 5)
481 *IM_BRGC6 = mclk_brg;
482# endif
483# if (MCLK_BRG == 6)
484 *IM_BRGC7 = mclk_brg;
485# endif
486# if (MCLK_BRG == 7)
487 *IM_BRGC8 = mclk_brg;
488# endif
489
490
491
492
493# if (SCLK_BRG == 0)
494 *IM_BRGC1 = sclk_brg;
495# endif
496# if (SCLK_BRG == 1)
497 *IM_BRGC2 = sclk_brg;
498# endif
499# if (SCLK_BRG == 2)
500 *IM_BRGC3 = sclk_brg;
501# endif
502# if (SCLK_BRG == 3)
503 *IM_BRGC4 = sclk_brg;
504# endif
505# if (SCLK_BRG == 4)
506 *IM_BRGC5 = sclk_brg;
507# endif
508# if (SCLK_BRG == 5)
509 *IM_BRGC6 = sclk_brg;
510# endif
511# if (SCLK_BRG == 6)
512 *IM_BRGC7 = sclk_brg;
513# endif
514# if (SCLK_BRG == 7)
515 *IM_BRGC8 = sclk_brg;
516# endif
517
518
519
520
521# if (LRCLK_BRG == 0)
522 *IM_BRGC1 = lrclk_brg;
523# endif
524# if (LRCLK_BRG == 1)
525 *IM_BRGC2 = lrclk_brg;
526# endif
527# if (LRCLK_BRG == 2)
528 *IM_BRGC3 = lrclk_brg;
529# endif
530# if (LRCLK_BRG == 3)
531 *IM_BRGC4 = lrclk_brg;
532# endif
533# if (LRCLK_BRG == 4)
534 *IM_BRGC5 = lrclk_brg;
535# endif
536# if (LRCLK_BRG == 5)
537 *IM_BRGC6 = lrclk_brg;
538# endif
539# if (LRCLK_BRG == 6)
540 *IM_BRGC7 = lrclk_brg;
541# endif
542# if (LRCLK_BRG == 7)
543 *IM_BRGC8 = lrclk_brg;
544# endif
545
546
547
548
549# if (MCLK_BRG == 0)
550 *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
551# endif
552# if (MCLK_BRG == 1)
553 *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
554# endif
555# if (MCLK_BRG == 2)
556 *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
557# endif
558# if (MCLK_BRG == 3)
559 *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
560# endif
561# if (MCLK_BRG == 4)
562 *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
563# endif
564# if (MCLK_BRG == 5)
565 *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
566# endif
567# if (MCLK_BRG == 6)
568 *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
569# endif
570# if (MCLK_BRG == 7)
571 *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
572# endif
573
574
575
576
577# if (SCLK_BRG == 0)
578 *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
579# endif
580# if (SCLK_BRG == 1)
581 *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
582# endif
583# if (SCLK_BRG == 2)
584 *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
585# endif
586# if (SCLK_BRG == 3)
587 *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
588# endif
589# if (SCLK_BRG == 4)
590 *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
591# endif
592# if (SCLK_BRG == 5)
593 *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
594# endif
595# if (SCLK_BRG == 6)
596 *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
597# endif
598# if (SCLK_BRG == 7)
599 *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
600# endif
601
602
603
604
605# if (LRCLK_BRG == 0)
606 *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
607# endif
608# if (LRCLK_BRG == 1)
609 *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
610# endif
611# if (LRCLK_BRG == 2)
612 *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
613# endif
614# if (LRCLK_BRG == 3)
615 *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
616# endif
617# if (LRCLK_BRG == 4)
618 *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
619# endif
620# if (LRCLK_BRG == 5)
621 *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
622# endif
623# if (LRCLK_BRG == 6)
624 *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
625# endif
626# if (LRCLK_BRG == 7)
627 *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
628# endif
629
630
631
632
633 if (flag) {
634 enable_interrupts();
635 }
636# else
637
638
639
640 Daq_BRG_Reset(MCLK_BRG);
641 Daq_BRG_Reset(SCLK_BRG);
642 Daq_BRG_Reset(LRCLK_BRG);
643# endif
644}
645
646void Daq_Start_Clocks(int sample_rate)
647
648{
649#ifdef TIGHTEN_UP_BRG_TIMING
650 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
651
652 register uint mclk_brg;
653 register uint sclk_brg;
654 register uint temp_lrclk_brg;
655 register uint real_lrclk_brg;
656 uint lrclk_brg;
657 unsigned long flags;
658 uint sclk_cnt;
659 uint delay_cnt;
660#endif
661
662# ifdef TIGHTEN_UP_BRG_TIMING
663
664
665
666# if (MCLK_BRG == 0)
667 mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
668# endif
669# if (MCLK_BRG == 1)
670 mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
671# endif
672# if (MCLK_BRG == 2)
673 mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
674# endif
675# if (MCLK_BRG == 3)
676 mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
677# endif
678# if (MCLK_BRG == 4)
679 mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
680# endif
681# if (MCLK_BRG == 5)
682 mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
683# endif
684# if (MCLK_BRG == 6)
685 mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
686# endif
687# if (MCLK_BRG == 7)
688 mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
689# endif
690
691
692
693
694# if (SCLK_BRG == 0)
695 sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
696# endif
697# if (SCLK_BRG == 1)
698 sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
699# endif
700# if (SCLK_BRG == 2)
701 sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
702# endif
703# if (SCLK_BRG == 3)
704 sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
705# endif
706# if (SCLK_BRG == 4)
707 sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
708# endif
709# if (SCLK_BRG == 5)
710 sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
711# endif
712# if (SCLK_BRG == 6)
713 sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
714# endif
715# if (SCLK_BRG == 7)
716 sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
717# endif
718
719
720
721
722# if (LRCLK_BRG == 0)
723 lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
724# endif
725# if (LRCLK_BRG == 1)
726 lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
727# endif
728# if (LRCLK_BRG == 2)
729 lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
730# endif
731# if (LRCLK_BRG == 3)
732 lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
733# endif
734# if (LRCLK_BRG == 4)
735 lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
736# endif
737# if (LRCLK_BRG == 5)
738 lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
739# endif
740# if (LRCLK_BRG == 6)
741 lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
742# endif
743# if (LRCLK_BRG == 7)
744 lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
745# endif
746
747
748 real_lrclk_brg = lrclk_brg;
749
750
751 sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1;
752
753
754 delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
755 if (DaqSampleRate == 43402) {
756 delay_cnt++;
757 }
758
759
760 temp_lrclk_brg = sclk_brg & ~0x00001FFE;
761
762
763 temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE;
764
765
766
767
768 flag = disable_interrupts();
769
770
771
772
773# if (MCLK_BRG == 0)
774 *IM_BRGC1 = mclk_brg;
775# endif
776# if (MCLK_BRG == 1)
777 *IM_BRGC2 = mclk_brg;
778# endif
779# if (MCLK_BRG == 2)
780 *IM_BRGC3 = mclk_brg;
781# endif
782# if (MCLK_BRG == 3)
783 *IM_BRGC4 = mclk_brg;
784# endif
785# if (MCLK_BRG == 4)
786 *IM_BRGC5 = mclk_brg;
787# endif
788# if (MCLK_BRG == 5)
789 *IM_BRGC6 = mclk_brg;
790# endif
791# if (MCLK_BRG == 6)
792 *IM_BRGC7 = mclk_brg;
793# endif
794# if (MCLK_BRG == 7)
795 *IM_BRGC8 = mclk_brg;
796# endif
797
798
799
800
801# if (SCLK_BRG == 0)
802 *IM_BRGC1 = sclk_brg;
803# endif
804# if (SCLK_BRG == 1)
805 *IM_BRGC2 = sclk_brg;
806# endif
807# if (SCLK_BRG == 2)
808 *IM_BRGC3 = sclk_brg;
809# endif
810# if (SCLK_BRG == 3)
811 *IM_BRGC4 = sclk_brg;
812# endif
813# if (SCLK_BRG == 4)
814 *IM_BRGC5 = sclk_brg;
815# endif
816# if (SCLK_BRG == 5)
817 *IM_BRGC6 = sclk_brg;
818# endif
819# if (SCLK_BRG == 6)
820 *IM_BRGC7 = sclk_brg;
821# endif
822# if (SCLK_BRG == 7)
823 *IM_BRGC8 = sclk_brg;
824# endif
825
826
827
828
829# if (LRCLK_BRG == 0)
830 *IM_BRGC1 = temp_lrclk_brg;
831# endif
832# if (LRCLK_BRG == 1)
833 *IM_BRGC2 = temp_lrclk_brg;
834# endif
835# if (LRCLK_BRG == 2)
836 *IM_BRGC3 = temp_lrclk_brg;
837# endif
838# if (LRCLK_BRG == 3)
839 *IM_BRGC4 = temp_lrclk_brg;
840# endif
841# if (LRCLK_BRG == 4)
842 *IM_BRGC5 = temp_lrclk_brg;
843# endif
844# if (LRCLK_BRG == 5)
845 *IM_BRGC6 = temp_lrclk_brg;
846# endif
847# if (LRCLK_BRG == 6)
848 *IM_BRGC7 = temp_lrclk_brg;
849# endif
850# if (LRCLK_BRG == 7)
851 *IM_BRGC8 = temp_lrclk_brg;
852# endif
853
854
855
856
857# if (LRCLK_BRG == 0)
858 *IM_BRGC1 = real_lrclk_brg;
859# endif
860# if (LRCLK_BRG == 1)
861 *IM_BRGC2 = real_lrclk_brg;
862# endif
863# if (LRCLK_BRG == 2)
864 *IM_BRGC3 = real_lrclk_brg;
865# endif
866# if (LRCLK_BRG == 3)
867 *IM_BRGC4 = real_lrclk_brg;
868# endif
869# if (LRCLK_BRG == 4)
870 *IM_BRGC5 = real_lrclk_brg;
871# endif
872# if (LRCLK_BRG == 5)
873 *IM_BRGC6 = real_lrclk_brg;
874# endif
875# if (LRCLK_BRG == 6)
876 *IM_BRGC7 = real_lrclk_brg;
877# endif
878# if (LRCLK_BRG == 7)
879 *IM_BRGC8 = real_lrclk_brg;
880# endif
881
882
883
884
885 if (flag) {
886 enable_interrupts();
887 }
888# else
889
890
891
892 Daq_BRG_Enable(LRCLK_BRG);
893 Daq_BRG_Enable(SCLK_BRG);
894 Daq_BRG_Enable(MCLK_BRG);
895# endif
896}
897
898void Daq_Display_Clocks(void)
899
900{
901 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
902 uint mclk_divisor;
903 uint sclk_divisor;
904
905 printf("\nBRG:\n");
906 if (immr->im_brgc4 != 0) {
907 printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n",
908 immr->im_brgc4,
909 (uint)&(immr->im_brgc4),
910 Daq_BRG_Get_Count(3),
911 Daq_BRG_Get_ExtClk(3),
912 Daq_BRG_Get_ExtClk_Description(3));
913 }
914 if (immr->im_brgc8 != 0) {
915 printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n",
916 immr->im_brgc8,
917 (uint)&(immr->im_brgc8),
918 Daq_BRG_Get_Count(7),
919 Daq_BRG_Get_ExtClk(7),
920 Daq_BRG_Get_ExtClk_Description(7));
921 }
922 if (immr->im_brgc6 != 0) {
923 printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n",
924 immr->im_brgc6,
925 (uint)&(immr->im_brgc6),
926 Daq_BRG_Get_Count(5),
927 Daq_BRG_Get_ExtClk(5),
928 Daq_BRG_Get_ExtClk_Description(5));
929 }
930 if (immr->im_brgc1 != 0) {
931 printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n",
932 immr->im_brgc1,
933 (uint)&(immr->im_brgc1),
934 Daq_BRG_Get_Count(0),
935 Daq_BRG_Get_ExtClk(0),
936 Daq_BRG_Get_ExtClk_Description(0));
937 }
938 if (immr->im_brgc2 != 0) {
939 printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n",
940 immr->im_brgc2,
941 (uint)&(immr->im_brgc2),
942 Daq_BRG_Get_Count(1),
943 Daq_BRG_Get_ExtClk(1),
944 Daq_BRG_Get_ExtClk_Description(1));
945 }
946 if (immr->im_brgc3 != 0) {
947 printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n",
948 immr->im_brgc3,
949 (uint)&(immr->im_brgc3),
950 Daq_BRG_Get_Count(2),
951 Daq_BRG_Get_ExtClk(2),
952 Daq_BRG_Get_ExtClk_Description(2));
953 }
954 if (immr->im_brgc5 != 0) {
955 printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
956 immr->im_brgc5,
957 (uint)&(immr->im_brgc5),
958 Daq_BRG_Get_Count(4),
959 Daq_BRG_Get_ExtClk(4),
960 Daq_BRG_Get_ExtClk_Description(4));
961 }
962 if (immr->im_brgc7 != 0) {
963 printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
964 immr->im_brgc7,
965 (uint)&(immr->im_brgc7),
966 Daq_BRG_Get_Count(6),
967 Daq_BRG_Get_ExtClk(6),
968 Daq_BRG_Get_ExtClk_Description(6));
969 }
970
971# ifdef RUN_SCLK_ON_BRG_INT
972 mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
973# else
974 mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
975# endif
976# ifdef RUN_LRCLK_ON_BRG_INT
977 sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
978# else
979 sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
980# endif
981
982 printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
983 printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
984 Daq_BRG_Rate(MCLK_BRG),
985 mclk_divisor,
986 mclk_divisor * sclk_divisor);
987# ifdef RUN_SCLK_ON_BRG_INT
988 printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
989 Daq_BRG_Rate(SCLK_BRG),
990 sclk_divisor);
991# else
992 printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
993 Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
994 sclk_divisor);
995# endif
996# ifdef RUN_LRCLK_ON_BRG_INT
997 printf("\tLRCLK %8d Hz\n",
998 Daq_BRG_Rate(LRCLK_BRG));
999# else
1000# ifdef RUN_SCLK_ON_BRG_INT
1001 printf("\tLRCLK %8d Hz\n",
1002 Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
1003# else
1004 printf("\tLRCLK %8d Hz\n",
1005 Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
1006# endif
1007# endif
1008 printf("\n");
1009}
1010
