1
2
3
4
5
6
7
8
9
10
11
12
13
14
15#include <common.h>
16#include <asm/io.h>
17#include <pci.h>
18#include <command.h>
19#include <config.h>
20#include <asm/byteorder.h>
21#include <part.h>
22#include <ide.h>
23#include <ata.h>
24#include <sata.h>
25
26#define DEBUG_SATA 0
27
28#define SATA_DECL
29#define DRV_DECL
30#include "ata_piix.h"
31
32
33#define PCI_SATA_BUS 0x00
34#define PCI_SATA_DEV 0x1f
35#define PCI_SATA_FUNC 0x02
36
37#define PCI_SATA_BASE1 0x10
38#define PCI_SATA_BASE2 0x14
39#define PCI_SATA_BASE3 0x18
40#define PCI_SATA_BASE4 0x1c
41#define PCI_SATA_BASE5 0x20
42#define PCI_PMR 0x90
43#define PCI_PI 0x09
44#define PCI_PCS 0x92
45#define PCI_DMA_CTL 0x48
46
47#define PORT_PRESENT (1<<0)
48#define PORT_ENABLED (1<<4)
49
50u32 bdf;
51u32 iobase1;
52u32 iobase2;
53u32 iobase3;
54u32 iobase4;
55u32 iobase5;
56
57int pci_sata_init(void)
58{
59 u32 bus = PCI_SATA_BUS;
60 u32 dev = PCI_SATA_DEV;
61 u32 fun = PCI_SATA_FUNC;
62 u16 cmd = 0;
63 u8 lat = 0, pcibios_max_latency = 0xff;
64 u8 pmr;
65 u8 pi;
66
67 bdf = PCI_BDF(bus, dev, fun);
68 pci_read_config_dword(bdf, PCI_SATA_BASE1, &iobase1);
69 pci_read_config_dword(bdf, PCI_SATA_BASE2, &iobase2);
70 pci_read_config_dword(bdf, PCI_SATA_BASE3, &iobase3);
71 pci_read_config_dword(bdf, PCI_SATA_BASE4, &iobase4);
72 pci_read_config_dword(bdf, PCI_SATA_BASE5, &iobase5);
73
74 if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
75 (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
76 (iobase5 == 0xFFFFFFFF)) {
77
78 printf("error no base addr for SATA controller\n");
79 return 1;
80 }
81
82 iobase1 &= 0xFFFFFFFE;
83 iobase2 &= 0xFFFFFFFE;
84 iobase3 &= 0xFFFFFFFE;
85 iobase4 &= 0xFFFFFFFE;
86 iobase5 &= 0xFFFFFFFE;
87
88
89 pci_read_config_byte(bdf, PCI_PMR, &pmr);
90 if (pmr > 1) {
91 puts("combined mode not supported\n");
92 return 1;
93 }
94
95 pci_read_config_byte(bdf, PCI_PI, &pi);
96 if ((pi & 0x05) != 0x05) {
97 puts("Sata is in Legacy mode\n");
98 return 1;
99 } else
100 puts("sata is in Native mode\n");
101
102
103 pci_read_config_word(bdf, PCI_COMMAND, &cmd);
104 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
105 pci_write_config_word(bdf, PCI_COMMAND, cmd);
106 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
107
108 if (lat < 16)
109 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
110 else if (lat > pcibios_max_latency)
111 lat = pcibios_max_latency;
112 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
113
114 return 0;
115}
116
117int sata_bus_probe(int port_no)
118{
119 int orig_mask, mask;
120 u16 pcs;
121
122 mask = (PORT_PRESENT << port_no);
123 pci_read_config_word(bdf, PCI_PCS, &pcs);
124 orig_mask = (int) pcs & 0xff;
125 if ((orig_mask & mask) != mask)
126 return 0;
127 else
128 return 1;
129}
130
131int init_sata(int dev)
132{
133 static int done;
134 u8 i, rv = 0;
135
136 if (!done)
137 done = 1;
138 else
139 return 0;
140
141 rv = pci_sata_init();
142 if (rv == 1) {
143 puts("pci initialization failed\n");
144 return 1;
145 }
146
147 port[0].port_no = 0;
148 port[0].ioaddr.cmd_addr = iobase1;
149 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
150 iobase2 | ATA_PCI_CTL_OFS;
151 port[0].ioaddr.bmdma_addr = iobase5;
152
153 port[1].port_no = 1;
154 port[1].ioaddr.cmd_addr = iobase3;
155 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
156 iobase4 | ATA_PCI_CTL_OFS;
157 port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
158
159 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
160 sata_port(&port[i].ioaddr);
161
162 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
163 if (!(sata_bus_probe(i))) {
164 port[i].port_state = 0;
165 printf("SATA#%d port is not present\n", i);
166 } else {
167 printf("SATA#%d port is present\n", i);
168 if (sata_bus_softreset(i))
169 port[i].port_state = 0;
170 else
171 port[i].port_state = 1;
172 }
173 }
174
175 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
176 u8 j, devno;
177
178 if (port[i].port_state == 0)
179 continue;
180 for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
181 sata_identify(i, j);
182 set_Feature_cmd(i, j);
183 devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
184 if ((sata_dev_desc[devno].lba > 0) &&
185 (sata_dev_desc[devno].blksz > 0)) {
186 dev_print(&sata_dev_desc[devno]);
187
188 init_part(&sata_dev_desc[devno]);
189 }
190 }
191 }
192 return 0;
193}
194
195static inline u8 sata_inb(unsigned long ioaddr)
196{
197 return inb(ioaddr);
198}
199
200static inline void sata_outb(unsigned char val, unsigned long ioaddr)
201{
202 outb(val, ioaddr);
203}
204
205static void output_data(struct sata_ioports *ioaddr, ulong * sect_buf,
206 int words)
207{
208 outsw(ioaddr->data_addr, sect_buf, words << 1);
209}
210
211static int input_data(struct sata_ioports *ioaddr, ulong * sect_buf, int words)
212{
213 insw(ioaddr->data_addr, sect_buf, words << 1);
214 return 0;
215}
216
217static void sata_cpy(unsigned char *dst, unsigned char *src, unsigned int len)
218{
219 unsigned char *end, *last;
220
221 last = dst;
222 end = src + len - 1;
223
224
225 if (len < 2)
226 goto OUT;
227
228
229 while ((*src) && (src < end) && (*src == ' '))
230 ++src;
231
232
233 while ((*src) && (src < end)) {
234 *dst++ = *src;
235 if (*src++ != ' ')
236 last = dst;
237 }
238OUT:
239 *last = '\0';
240}
241
242int sata_bus_softreset(int num)
243{
244 u8 dev = 0, status = 0, i;
245
246 port[num].dev_mask = 0;
247
248 for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
249 if (!(sata_devchk(&port[num].ioaddr, i))) {
250 debug("dev_chk failed for dev#%d\n", i);
251 } else {
252 port[num].dev_mask |= (1 << i);
253 debug("dev_chk passed for dev#%d\n", i);
254 }
255 }
256
257 if (!(port[num].dev_mask)) {
258 printf("no devices on port%d\n", num);
259 return 1;
260 }
261
262 dev_select(&port[num].ioaddr, dev);
263
264 port[num].ctl_reg = 0x08;
265 sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
266 udelay(10);
267 sata_outb(port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
268 udelay(10);
269 sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
270
271
272
273
274
275
276
277
278
279
280 mdelay(150);
281 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 300);
282 while ((status & ATA_BUSY)) {
283 mdelay(100);
284 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 3);
285 }
286
287 if (status & ATA_BUSY)
288 printf("ata%u is slow to respond,plz be patient\n", num);
289
290 while ((status & ATA_BUSY)) {
291 mdelay(100);
292 status = sata_chk_status(&port[num].ioaddr);
293 }
294
295 if (status & ATA_BUSY) {
296 printf("ata%u failed to respond : bus reset failed\n", num);
297 return 1;
298 }
299 return 0;
300}
301
302void sata_identify(int num, int dev)
303{
304 u8 cmd = 0, status = 0;
305 u8 devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
306 u16 iobuf[ATA_SECT_SIZE];
307 u64 n_sectors = 0;
308 u8 mask = 0;
309
310 memset(iobuf, 0, sizeof(iobuf));
311 hd_driveid_t *iop = (hd_driveid_t *) iobuf;
312
313 if (dev == 0)
314 mask = 0x01;
315 else
316 mask = 0x02;
317
318 if (!(port[num].dev_mask & mask)) {
319 printf("dev%d is not present on port#%d\n", dev, num);
320 return;
321 }
322
323 printf("port=%d dev=%d\n", num, dev);
324
325 dev_select(&port[num].ioaddr, dev);
326
327 status = 0;
328 cmd = ATA_CMD_IDENT;
329 sata_outb(cmd, port[num].ioaddr.command_addr);
330 sata_inb(port[num].ioaddr.altstatus_addr);
331 udelay(10);
332
333 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 1000);
334 if (status & ATA_ERR) {
335 puts("\ndevice not responding\n");
336 port[num].dev_mask &= ~mask;
337 return;
338 }
339
340 input_data(&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
341
342 debug("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
343 "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
344 iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
345 iobuf[87], iobuf[88]);
346
347
348 if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
349 debug("ata%u: no dma/lba\n", num);
350 ata_dump_id(iobuf);
351
352 if (ata_id_has_lba48(iobuf))
353 n_sectors = ata_id_u64(iobuf, 100);
354 else
355 n_sectors = ata_id_u32(iobuf, 60);
356 debug("no. of sectors %u\n", ata_id_u64(iobuf, 100));
357 debug("no. of sectors %u\n", ata_id_u32(iobuf, 60));
358
359 if (n_sectors == 0) {
360 port[num].dev_mask &= ~mask;
361 return;
362 }
363
364 sata_cpy((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
365 sizeof(sata_dev_desc[devno].revision));
366 sata_cpy((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
367 sizeof(sata_dev_desc[devno].vendor));
368 sata_cpy((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
369 sizeof(sata_dev_desc[devno].product));
370 strswab(sata_dev_desc[devno].revision);
371 strswab(sata_dev_desc[devno].vendor);
372
373 if ((iop->config & 0x0080) == 0x0080)
374 sata_dev_desc[devno].removable = 1;
375 else
376 sata_dev_desc[devno].removable = 0;
377
378 sata_dev_desc[devno].lba = iop->lba_capacity;
379 debug("lba=0x%x", sata_dev_desc[devno].lba);
380
381#ifdef CONFIG_LBA48
382 if (iop->command_set_2 & 0x0400) {
383 sata_dev_desc[devno].lba48 = 1;
384 lba = (unsigned long long) iop->lba48_capacity[0] |
385 ((unsigned long long) iop->lba48_capacity[1] << 16) |
386 ((unsigned long long) iop->lba48_capacity[2] << 32) |
387 ((unsigned long long) iop->lba48_capacity[3] << 48);
388 } else {
389 sata_dev_desc[devno].lba48 = 0;
390 }
391#endif
392
393
394 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
395 sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
396 sata_dev_desc[devno].log2blksz = LOG2(sata_dev_desc[devno].blksz);
397 sata_dev_desc[devno].lun = 0;
398}
399
400void set_Feature_cmd(int num, int dev)
401{
402 u8 mask = 0x00, status = 0;
403
404 if (dev == 0)
405 mask = 0x01;
406 else
407 mask = 0x02;
408
409 if (!(port[num].dev_mask & mask)) {
410 debug("dev%d is not present on port#%d\n", dev, num);
411 return;
412 }
413
414 dev_select(&port[num].ioaddr, dev);
415
416 sata_outb(SETFEATURES_XFER, port[num].ioaddr.feature_addr);
417 sata_outb(XFER_PIO_4, port[num].ioaddr.nsect_addr);
418 sata_outb(0, port[num].ioaddr.lbal_addr);
419 sata_outb(0, port[num].ioaddr.lbam_addr);
420 sata_outb(0, port[num].ioaddr.lbah_addr);
421
422 sata_outb(ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
423 sata_outb(ATA_CMD_SETF, port[num].ioaddr.command_addr);
424
425 udelay(50);
426 mdelay(150);
427
428 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 5000);
429 if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
430 printf("Error : status 0x%02x\n", status);
431 port[num].dev_mask &= ~mask;
432 }
433}
434
435void sata_port(struct sata_ioports *ioport)
436{
437 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
438 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
439 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
440 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
441 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
442 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
443 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
444 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
445 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
446 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
447}
448
449int sata_devchk(struct sata_ioports *ioaddr, int dev)
450{
451 u8 nsect, lbal;
452
453 dev_select(ioaddr, dev);
454
455 sata_outb(0x55, ioaddr->nsect_addr);
456 sata_outb(0xaa, ioaddr->lbal_addr);
457
458 sata_outb(0xaa, ioaddr->nsect_addr);
459 sata_outb(0x55, ioaddr->lbal_addr);
460
461 sata_outb(0x55, ioaddr->nsect_addr);
462 sata_outb(0xaa, ioaddr->lbal_addr);
463
464 nsect = sata_inb(ioaddr->nsect_addr);
465 lbal = sata_inb(ioaddr->lbal_addr);
466
467 if ((nsect == 0x55) && (lbal == 0xaa))
468 return 1;
469 else
470 return 0;
471}
472
473void dev_select(struct sata_ioports *ioaddr, int dev)
474{
475 u8 tmp = 0;
476
477 if (dev == 0)
478 tmp = ATA_DEVICE_OBS;
479 else
480 tmp = ATA_DEVICE_OBS | ATA_DEV1;
481
482 sata_outb(tmp, ioaddr->device_addr);
483 sata_inb(ioaddr->altstatus_addr);
484 udelay(5);
485}
486
487u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max)
488{
489 u8 status;
490
491 do {
492 udelay(1000);
493 status = sata_chk_status(ioaddr);
494 max--;
495 } while ((status & bits) && (max > 0));
496
497 return status;
498}
499
500u8 sata_chk_status(struct sata_ioports *ioaddr)
501{
502 return sata_inb(ioaddr->status_addr);
503}
504
505
506ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buff)
507{
508 ulong n = 0, *buffer = (ulong *)buff;
509 u8 dev = 0, num = 0, mask = 0, status = 0;
510
511#ifdef CONFIG_LBA48
512 unsigned char lba48 = 0;
513
514 if (blknr & 0x0000fffff0000000) {
515 if (!sata_dev_desc[devno].lba48) {
516 printf("Drive doesn't support 48-bit addressing\n");
517 return 0;
518 }
519
520 lba48 = 1;
521 }
522#endif
523
524 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
525
526 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
527 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
528 else
529 dev = device;
530
531 if (dev == 0)
532 mask = 0x01;
533 else
534 mask = 0x02;
535
536 if (!(port[num].dev_mask & mask)) {
537 printf("dev%d is not present on port#%d\n", dev, num);
538 return 0;
539 }
540
541
542 dev_select(&port[num].ioaddr, dev);
543
544 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
545 if (status & ATA_BUSY) {
546 printf("ata%u failed to respond\n", port[num].port_no);
547 return n;
548 }
549 while (blkcnt-- > 0) {
550 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
551 if (status & ATA_BUSY) {
552 printf("ata%u failed to respond\n", 0);
553 return n;
554 }
555#ifdef CONFIG_LBA48
556 if (lba48) {
557
558 sata_outb(0, port[num].ioaddr.nsect_addr);
559 sata_outb((blknr >> 24) & 0xFF,
560 port[num].ioaddr.lbal_addr);
561 sata_outb((blknr >> 32) & 0xFF,
562 port[num].ioaddr.lbam_addr);
563 sata_outb((blknr >> 40) & 0xFF,
564 port[num].ioaddr.lbah_addr);
565 }
566#endif
567 sata_outb(1, port[num].ioaddr.nsect_addr);
568 sata_outb(((blknr) >> 0) & 0xFF,
569 port[num].ioaddr.lbal_addr);
570 sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
571 sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
572
573#ifdef CONFIG_LBA48
574 if (lba48) {
575 sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
576 sata_outb(ATA_CMD_READ_EXT,
577 port[num].ioaddr.command_addr);
578 } else
579#endif
580 {
581 sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
582 port[num].ioaddr.device_addr);
583 sata_outb(ATA_CMD_READ,
584 port[num].ioaddr.command_addr);
585 }
586
587 mdelay(50);
588
589 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
590
591 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
592 != ATA_STAT_DRQ) {
593 u8 err = 0;
594
595 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
596 device, (ulong) blknr, status);
597 err = sata_inb(port[num].ioaddr.error_addr);
598 printf("Error reg = 0x%x\n", err);
599 return n;
600 }
601 input_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
602 sata_inb(port[num].ioaddr.altstatus_addr);
603 udelay(50);
604
605 ++n;
606 ++blknr;
607 buffer += ATA_SECTORWORDS;
608 }
609 return n;
610}
611
612ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buff)
613{
614 ulong n = 0, *buffer = (ulong *)buff;
615 unsigned char status = 0, num = 0, dev = 0, mask = 0;
616
617#ifdef CONFIG_LBA48
618 unsigned char lba48 = 0;
619
620 if (blknr & 0x0000fffff0000000) {
621 if (!sata_dev_desc[devno].lba48) {
622 printf("Drive doesn't support 48-bit addressing\n");
623 return 0;
624 }
625
626 lba48 = 1;
627 }
628#endif
629
630 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
631
632 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
633 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
634 else
635 dev = device;
636
637 if (dev == 0)
638 mask = 0x01;
639 else
640 mask = 0x02;
641
642
643 dev_select(&port[num].ioaddr, dev);
644
645 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
646 if (status & ATA_BUSY) {
647 printf("ata%u failed to respond\n", port[num].port_no);
648 return n;
649 }
650
651 while (blkcnt-- > 0) {
652 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
653 if (status & ATA_BUSY) {
654 printf("ata%u failed to respond\n",
655 port[num].port_no);
656 return n;
657 }
658#ifdef CONFIG_LBA48
659 if (lba48) {
660
661 sata_outb(0, port[num].ioaddr.nsect_addr);
662 sata_outb((blknr >> 24) & 0xFF,
663 port[num].ioaddr.lbal_addr);
664 sata_outb((blknr >> 32) & 0xFF,
665 port[num].ioaddr.lbam_addr);
666 sata_outb((blknr >> 40) & 0xFF,
667 port[num].ioaddr.lbah_addr);
668 }
669#endif
670 sata_outb(1, port[num].ioaddr.nsect_addr);
671 sata_outb((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
672 sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
673 sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
674#ifdef CONFIG_LBA48
675 if (lba48) {
676 sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
677 sata_outb(ATA_CMD_WRITE_EXT,
678 port[num].ioaddr.command_addr);
679 } else
680#endif
681 {
682 sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
683 port[num].ioaddr.device_addr);
684 sata_outb(ATA_CMD_WRITE,
685 port[num].ioaddr.command_addr);
686 }
687
688 mdelay(50);
689
690 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
691 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
692 != ATA_STAT_DRQ) {
693 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
694 device, (ulong) blknr, status);
695 return n;
696 }
697
698 output_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
699 sata_inb(port[num].ioaddr.altstatus_addr);
700 udelay(50);
701
702 ++n;
703 ++blknr;
704 buffer += ATA_SECTORWORDS;
705 }
706 return n;
707}
708
709int scan_sata(int dev)
710{
711 return 0;
712}
713
