LXR uboot/include/configs/CPCIISER4.h

   1/*
   2 * (C) Copyright 2001-2003
   3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*
   9 * board/config.h - configuration options, board specific
  10 */
  11
  12#ifndef __CONFIG_H
  13#define __CONFIG_H
  14
  15/*
  16 * High Level Configuration Options
  17 * (easy to change)
  18 */
  19
  20#define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  21#define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  22#define CONFIG_CPCIISER4        1       /* ...on a CPCIISER4 board      */
  23
  24#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  25
  26#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  27
  28#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  29
  30#define CONFIG_BAUDRATE         9600
  31#define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  32
  33#undef  CONFIG_BOOTARGS
  34#define CONFIG_BOOTCOMMAND      "bootm fff00000"
  35
  36#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  37#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  38
  39#define CONFIG_PPC4xx_EMAC
  40#define CONFIG_MII              1       /* MII PHY management           */
  41#define CONFIG_PHY_ADDR         0       /* PHY address                  */
  42#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  43
  44
  45/*
  46 * BOOTP options
  47 */
  48#define CONFIG_BOOTP_BOOTFILESIZE
  49#define CONFIG_BOOTP_BOOTPATH
  50#define CONFIG_BOOTP_GATEWAY
  51#define CONFIG_BOOTP_HOSTNAME
  52
  53
  54/*
  55 * BOOTP options
  56 */
  57#define CONFIG_BOOTP_BOOTFILESIZE
  58#define CONFIG_BOOTP_BOOTPATH
  59#define CONFIG_BOOTP_GATEWAY
  60#define CONFIG_BOOTP_HOSTNAME
  61
  62
  63/*
  64 * Command line configuration.
  65 */
  66#include <config_cmd_default.h>
  67
  68#define CONFIG_CMD_PCI
  69#define CONFIG_CMD_IRQ
  70#define CONFIG_CMD_MII
  71#define CONFIG_CMD_ELF
  72#define CONFIG_CMD_EEPROM
  73
  74
  75#undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  76
  77#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  78
  79/*
  80 * Miscellaneous configurable options
  81 */
  82#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  83#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  84#if defined(CONFIG_CMD_KGDB)
  85#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  86#else
  87#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  88#endif
  89#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  90#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  91#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  92
  93#define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
  94
  95#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  96#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  97
  98#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  99#define CONFIG_SYS_NS16550
 100#define CONFIG_SYS_NS16550_SERIAL
 101#define CONFIG_SYS_NS16550_REG_SIZE     1
 102#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 103
 104#define CONFIG_SYS_EXT_SERIAL_CLOCK     1843200  /* use external serial clock   */
 105
 106/* The following table includes the supported baudrates */
 107#define CONFIG_SYS_BAUDRATE_TABLE       \
 108        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 109         57600, 115200, 230400, 460800, 921600 }
 110
 111#define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 112#define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 113
 114#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 115
 116#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 117
 118/*-----------------------------------------------------------------------
 119 * PCI stuff
 120 *-----------------------------------------------------------------------
 121 */
 122#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 123#define PCI_HOST_FORCE  1               /* configure as pci host        */
 124#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 125
 126#define CONFIG_PCI                      /* include pci support          */
 127#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 128#define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 129#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 130                                        /* resource configuration       */
 131
 132#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 133#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404   /* PCI Device ID: CPCI-ISER4    */
 134#define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 135#define CONFIG_SYS_PCI_PTM1MS   0xff000001      /* 16MB, enable hard-wired to 1 */
 136#define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 137#define CONFIG_SYS_PCI_PTM2LA   0xffe00000      /* point to flash               */
 138#define CONFIG_SYS_PCI_PTM2MS   0xffe00001      /* 2MB, enable                  */
 139#define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 140
 141/*-----------------------------------------------------------------------
 142 * Start addresses for the final memory configuration
 143 * (Set up by the startup code)
 144 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 145 */
 146#define CONFIG_SYS_SDRAM_BASE           0x00000000
 147#define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 148#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 149#define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 150#define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 151
 152/*
 153 * For booting Linux, the board info and command line data
 154 * have to be in the first 8 MB of memory, since this is
 155 * the maximum mapped by the Linux kernel during initialization.
 156 */
 157#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 158/*-----------------------------------------------------------------------
 159 * FLASH organization
 160 */
 161#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 162#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 163
 164#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 165#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 166
 167#define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 168#define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 169#define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 170/*
 171 * The following defines are added for buggy IOP480 byte interface.
 172 * All other boards should use the standard values (CPCI405 etc.)
 173 */
 174#define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 175#define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 176#define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 177
 178#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 179
 180/*-----------------------------------------------------------------------
 181 * I2C EEPROM (CAT24WC08) for environment
 182 */
 183#define CONFIG_SYS_I2C
 184#define CONFIG_SYS_I2C_PPC4XX
 185#define CONFIG_SYS_I2C_PPC4XX_CH0
 186#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 187#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 188
 189#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 190#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 191/* mask of address bits that overflow into the "EEPROM chip address"    */
 192#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 193#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 194                                        /* 16 byte page write mode using*/
 195                                        /* last 4 bits of the address   */
 196#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 197
 198#define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 199#define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 200#define CONFIG_ENV_SIZE         0x300   /* 768 bytes may be used for env vars */
 201                                   /* total size of a CAT24WC08 is 1024 bytes */
 202
 203/*
 204 * Init Memory Controller:
 205 *
 206 * BR0/1 and OR0/1 (FLASH)
 207 */
 208
 209#define FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank #0        */
 210#define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 211
 212/*-----------------------------------------------------------------------
 213 * External Bus Controller (EBC) Setup
 214 */
 215
 216/* Memory Bank 0 (Flash Bank 0) initialization                                  */
 217#define CONFIG_SYS_EBC_PB0AP            0x92015480
 218#define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 219
 220/* Memory Bank 1 (Uart 8bit) initialization                                     */
 221#define CONFIG_SYS_EBC_PB1AP            0x01000480  /* TWT=2,TH=2,no Ready,BEM=0,SOR=1  */
 222#define CONFIG_SYS_EBC_PB1CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 223
 224/* Memory Bank 2 (Uart 32bit) initialization                                    */
 225#define CONFIG_SYS_EBC_PB2AP            0x000004c0  /* no Ready, BEM=1                  */
 226#define CONFIG_SYS_EBC_PB2CR            0xF011C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
 227
 228/* Memory Bank 3 (FPGA Reset) initialization                                    */
 229#define CONFIG_SYS_EBC_PB3AP            0x010004C0  /* no Ready, BEM=1                  */
 230#define CONFIG_SYS_EBC_PB3CR            0xF021A000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
 231
 232/*-----------------------------------------------------------------------
 233 * Definitions for initial stack pointer and data area (in DPRAM)
 234 */
 235#define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 236#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 237#define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM            */
 238#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 239#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 240
 241#endif  /* __CONFIG_H */
 242